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? 2003 microchip technology inc. ds39599c pic18f2220/2320/4220/4320 data sheet 28/40/44-pin high-performance, enhanced flash microcontrollers with 10-bit a/d and nanowatt technology
ds39599c-page ii ? 2003 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , mplab, pic, picmicro, picstart, pro mate and powersmart are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, micro id , mxdev, mxlab, picmaster, seeval and the embedded control solutions company are registered trademarks of micr ochip technology incorporated in the u.s.a. application maestro, dspicdem, dspicdem.net, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, powercal, powerinfo, powermate, powertool, rflab, rfpic, select mode, smartsensor, smartshunt, smar ttel and total endurance are trademarks of microchip technology incorporated in the u.s.a. and other countries. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned he rein are property of their respective companies. ? 2003, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip's data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semicondu ctor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are comm itted to continuously improving t he code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
? 2003 microchip technology inc. ds39599c-page 1 low-power features: power managed modes: - run: cpu on, peripherals on - idle: cpu off, peripherals on - sleep: cpu off, peripherals off power consumption modes: - pri_run: 150 a, 1 mhz, 2v - pri_idle: 37 a, 1 mhz, 2v - sec_run: 14 a, 32 khz, 2v - sec_idle: 5.8 a, 32 khz, 2v - rc_run: 110 a, 1 mhz, 2v - rc_idle: 52 a, 1 mhz, 2v - sleep: 0.1 a, 1 mhz, 2v timer1 oscillator: 1.1 a, 32 khz, 2v watchdog timer: 2.1 a two-speed oscillator start-up oscillators: four crystal modes: - lp, xt, hs: up to 25 mhz - hspll: 4-10 mhz (16-40 mhz internal) two external rc modes, up to 4 mhz two external clock modes, up to 40 mhz internal oscillator block: - 8 user selectable frequencies: 31 khz, 125 khz, 250 khz, 500 khz, 1 mhz, 2 mhz, 4 mhz, 8 mhz - 125 khz-8 mhz calibrated to 1% - two modes select one or two i/o pins - osctune ? allows user to shift frequency secondary oscillator using timer1 @ 32 khz fail-safe clock monitor - allows for safe shutdown if peripheral clock stops peripheral highlights: high current sink/source 25 ma/25 ma three external interrupts up to 2 capture/compare/pwm (ccp) modules: - capture is 16-bit, max. resolution is 6.25 ns (t cy /16) - compare is 16-bit, max. resolution is 100 ns (t cy ) - pwm output: pwm resolution is 1 to 10-bit enhanced capture/compare/pwm (eccp) module: - one, two or four pwm outputs - selectable polarity - programmable dead-time - auto-shutdown and auto-restart compatible 10-bit, up to 13-channel analog-to-digital converter module (a/d) with programmable acquisition time dual analog comparators addressable usart module: - rs-232 operation using internal oscillator block (no external crystal required) special microcontroller features: 100,000 erase/write cycle enhanced flash program memory typical 1,000,000 erase/write cycle data eeprom memory typical flash/data eeprom retention: > 40 years self-programmable under software control priority levels for interrupts 8 x 8 single-cycle hardware multiplier extended watchdog timer (wdt): - programmable period from 41 ms to 131s - 2% stability over v dd and temperature single-supply 5v in-circuit serial programming? (icsp?) via two pins in-circuit debug (icd) via two pins wide operating voltage range: 2.0v to 5.5v device program memory data memory i/o 10-bit a/d (ch) ccp/ eccp (pwm) mssp usart comparators timers 8/16-bit flash (bytes) # single word instructions sram (bytes) eeprom (bytes) spi? master i 2 c? pic18f2220 4096 2048 512 256 25 10 2/0 y y y 2 2/3 pic18f2320 8192 4096 512 256 25 10 2/0 y y y 2 2/3 pic18f4220 4096 2048 512 256 36 13 1/1 y y y 2 2/3 pic18f4320 8192 4096 512 256 36 13 1/1 y y y 2 2/3 28/40/44-pin high-p erformance, enhanced flash mcus with 10-bit a/d and nanowatt technology pic18f2220/2320/4220/4320
pic18f2220/2320/4220/4320 ds39599c-page 2 ? 2003 microchip technology inc. pin diagrams rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0 rb3/an9/ccp2* rb2/an8/int2 rb1/an10/int1 rb0/an12/int0 v dd v ss rd7/psp7/p1d rd6/psp6/p1c rd5/psp5/p1b rd4/psp4 rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out re0/an5/rd re1/an6/wr re2/an7/cs v dd v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi/ccp2* rc2/ccp1/p1a rc3/sck/scl rd0/psp0 rd1/psp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pic18f4320 pic18f2320 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 mclr /v pp /re3 ra0/an0 ra1/an1 ra2/an2/v ref -/cv ref ra3/an3/v ref + ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out v ss osc1/clki/ra7 osc2/clko/ra6 rc0/t1oso/t1cki rc1/t1osi/ccp2 * rc2/ccp1/p1a rc3/sck/scl rb7/kbi3/pgd rb6//kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0 rb3/an9/ccp2 * rb2/an8/int2 rb1/an10/int1 rb0/an12/int0 v dd v ss rc7/rx/dt rc6/tx/ck rc5/sdo rc4/sdi/sda pdip spdip, soic note: pin compatible with 40-pin pic16c7x devices. pic18f4220 pic18f2220 * rb3 is the alternate pin for the ccp2 pin multiplexing.
? 2003 microchip technology inc. ds39599c-page 3 pic18f2220/2320/4220/4320 pin diagrams (cont.?d) 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4220 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 nc rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 * nc nc rc0/t1oso/t1cki osc2/clko/ra6 osc1/clki/ra7 v ss v dd re2/an7/cs re1/an6/wr re0/an5/rd ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d v ss v dd rb0/an12/int0 rb1/an10/int1 rb2/an8/int2 rb3/an9/ccp2* tqfp * rb3 is the alternate pin for the ccp2 pin multiplexing. pic18f4320 10 11 2 3 4 5 6 1 18 19 20 21 22 12 13 14 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic18f4220 37 ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 mclr /v pp /re3 rb3/an9/ccp2* rb7/kbi3/pgd rb6/kbi2/pgc rb5/kbi1/pgm rb4/an11/kbi0 nc rc6/tx/ck rc5/sdo rc4/sdi/sda rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3/sck/scl rc2/ccp1/p1a rc1/t1osi/ccp2 * rc0/t1oso/t1cki osc2/clko/ra6 osc1/clki/ra7 v ss v ss v dd nc re2/an7/cs re1/an6/wr re0/an5/rd ra5/an4/ss /lvdin/c2out ra4/t0cki/c1out rc7/rx/dt rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d v ss v dd v dd rb0/an12/int0 rb1/an10/int1 rb2/an8/int2 qfn pic18f4320 * rb3 is the alternate pin for the ccp2 pin multiplexing.
pic18f2220/2320/4220/4320 ds39599c-page 4 ? 2003 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ................................................................................................... ......................................................... 19 3.0 power managed modes ......................................................................................................... .................................................... 29 4.0 reset ....................................................................................................................... ................................................................... 43 5.0 memory organization ......................................................................................................... ........................................................ 53 6.0 flash program memory........................................................................................................ ...................................................... 71 7.0 data eeprom memory .......................................................................................................... ................................................... 81 8.0 8 x 8 hardware multiplier ................................................................................................... ........................................................ 85 9.0 interrupts .................................................................................................................. .................................................................. 87 10.0 i/o ports .................................................................................................................. ................................................................. 101 11.0 timer0 module .............................................................................................................. ........................................................... 117 12.0 timer1 module .............................................................................................................. ........................................................... 121 13.0 timer2 module .............................................................................................................. ........................................................... 127 14.0 timer3 module .............................................................................................................. ........................................................... 129 15.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 133 16.0 enhanced capture/compare/pwm (eccp) module................................................................................. ............................... 141 17.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 155 18.0 addressable universal synchronous asynchr onous receiver transmitter (usart)................................................ .............. 195 19.0 10-bit analog-to-digital converter (a/d) module ............................................................................ .......................................... 211 20.0 comparator module.......................................................................................................... ........................................................ 221 21.0 comparator voltage reference module ........................................................................................ ........................................... 227 22.0 low-voltage detect ......................................................................................................... ......................................................... 231 23.0 special features of the cpu ................................................................................................ .................................................... 237 24.0 instruction set summary .................................................................................................... ...................................................... 255 25.0 development support........................................................................................................ ....................................................... 299 26.0 electrical characteristics ................................................................................................. ......................................................... 305 27.0 dc and ac characteristics graphs and tables ................................................................................ ....................................... 343 28.0 packaging information...................................................................................................... ........................................................ 361 appendix a: revision history................................................................................................... .......................................................... 369 appendix b: device differences................................................................................................. ........................................................ 369 appendix c: conversion considerations .......................................................................................... ................................................. 370 appendix d: migration from baseline to enhanced devices........................................................................ ...................................... 370 appendix e: migration from mid-range to enhanced devices ....................................................................... ................................... 371 appendix f: migration from high-end to enhanced devices ........................................................................ ..................................... 371 index .......................................................................................................................... ........................................................................ 373 on-line support................................................................................................................ ................................................................. 383 systems information and upgrade hot line ....................................................................................... ............................................... 383 reader response ................................................................................................................ .............................................................. 384 pic18f2220/2320/4220/4320 product identification system ........................................................................ .................................... 385
? 2003 microchip technology inc. ds39599c-page 5 pic18f2220/2320/4220/4320 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de literature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic18f2220/2320/4220/4320 ds39599c-page 6 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 7 pic18f2220/2320/4220/4320 1.0 device overview this document contains device specific information for the following devices: this family offers the advantages of all pic18 micro- controllers ? namely, high computational performance at an economical price with the addition of high- endurance enhanced flash program memory. on top of these features, the pic18f2220/2320/4220/4320 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 new core features 1.1.1 nanowatt technology all of the devices in the pic18f2220/2320/4220/4320 family incorporate a range of features that can signifi- cantly reduce power consumption during operation. key items include: alternate run modes: by clocking the controller from the timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. multiple idle modes: the controller can also run with its cpu core disabled, but the peripherals are still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. on-the-fly mode switching: the power managed modes are invoked by user code during operation, allowing the user to incorporate power saving ideas into their application?s software design. lower consumption in key modules: the power requirements for both timer1 and the watchdog timer have been reduced by up to 80%, with typical values of 1.8 and 2.2 a, respectively. 1.1.2 multiple oscillator options and features all of the devices in the pic18f2220/2320/4220/4320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. these include: four crystal modes using crystals or ceramic resonators. two external clock modes offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input with the second pin reassigned as general i/o). two external rc oscillator modes with the same pin options as the external clock modes. an internal oscillator block, which provides a 31 khz intrc clock and an 8 mhz clock with 6 program selectable divider ratios (4 mhz to 125 khz) for a total of 8 clock frequencies. besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. this allows for code execu- tion during what would other wise be the clock start-up interval and can even allow an application to perform routine background activities and return to sleep without returning to full power operation. 1.2 other special features memory endurance: the enhanced flash cells for both program memory and data eeprom are rated to last for many thousands of erase/write cycles ? up to 100,000 for program memory and 1,000,000 for eeprom. data retention without refresh is conservatively estimated to be greater than 40 years. self-programmability: these devices can write to their own program memory spaces under internal software control. by using a bootloader routine located in the protected boot block at the top of pro- gram memory, it becomes possible to create an application that can update itself in the field. enhanced ccp module: in pwm mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. other features include auto-shutdown for disabling pwm outputs on interrupt or other select conditions and auto-restart to reactivate outputs once the condition has cleared. addressable usart: this serial communication module is capable of standard rs-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a chan- nel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature. pic18f2220 pic18f4220 pic18f2320 pic18f4320
pic18f2220/2320/4220/4320 ds39599c-page 8 ? 2003 microchip technology inc. 1.3 details on individual family members devices in the pic18f2220/2320/4220/4320 family are available in 28-pin (pic18f2x20) and 40/44-pin (pic18f4x20) packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in five ways: 1. flash program memory (4 kbytes for pic18fx220 devices, 8 kbytes for pic18fx320) 2. a/d channels (10 for pic18f2x20 devices, 13 for pic18f4x20 devices) 3. i/o ports (3 bidirectional ports and 1 input only port on pic18f2x20 devices, 5 bidirectional ports on pic18f4x20 devices) 4. ccp and enhanced ccp implementation (pic18f2x20 devices have 2 standard ccp modules, pic18f4x20 devices have one standard ccp module and one eccp module) 5. parallel slave port (present only on pic18f4x20 devices) all other features for devices in this family are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2 and table 1-3. table 1-1: device features features pic18f2220 pic18f2320 pic18f4220 pic18f4320 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 4096 8192 4096 8192 program memory (instructions) 2048 4096 2048 4096 data memory (bytes) 512 512 512 512 data eeprom memory (bytes) 256 256 256 256 interrupt sources 19 19 20 20 i/o ports ports a, b, c (e) ports a, b, c (e) ports a, b, c, d, e ports a, b, c, d, e timers 4 4 4 4 capture/compare/pwm modules 2 2 1 1 enhanced capture/ compare/pwm modules 0011 serial communications mssp, addressable usart mssp, addressable usart mssp, addressable usart mssp, addressable usart parallel communications (psp) no no yes yes 10-bit analog-to-digital module 10 input channels 10 input channels 13 input channels 13 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions 75 instructions 75 instructions 75 instructions packages 28-pin spdip 28-pin soic 28-pin spdip 28-pin soic 40-pin pdip 44-pin tqfp 44-pin qfn 40-pin pdip 44-pin tqfp 44-pin qfn
? 2003 microchip technology inc. ds39599c-page 9 pic18f2220/2320/4220/4320 figure 1-1: pic18f2220/2320 block diagram instruction decode & control porta portb portc ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out rc0/t1oso/t1cki rc1/t1osi/ccp2 (1) rc2/ccp1/p1a rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt addressable ccp1 synchronous timer0 timer1 timer2 serial port ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 converter data latch data ram address latch address<12> 12 (2) bsr fsr0 fsr1 fsr2 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bit op 8 8 alu<8> 8 address latch program memory (4 kbytes) data latch 20 21 21 16 8 8 8 inc/dec logic 21 8 data bus<8> 8 instruction 12 3 rom latch timer3 ccp2 bank0, f pclatu pcu osc2/clko/ra6 (3) usart master 8 register table latch ta b l e p o i n t e r < 2 > inc/dec logic rb0/an12/int0 rb4/an11/kbi0 rb1/an10/int1 rb2/an8/int2 rb3/an9/ccp2 (1) rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd data eeprom osc1/clki/ra7 (3) decode 10-bit a/d porte re3 (2) power-up timer power-on reset watchdog timer mclr (2) v dd , v ss brown-out reset precision reference voltage low-voltage programming in-circuit debugger oscillator start-up timer internal osc1 (3) osc2 (3) t1osi t1oso int rc oscillator fail-safe clock monitor note 1: optional multiplexing of ccp2 input/output with rb3 is enabled by selection of the ccpmx2 configuration bit. 2: re3 is available only when the mclr resets are disabled. 3: osc1, osc2, clki and clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. 8 oscillator block (512 bytes) (8- or 16-bit) (16-bit) (8-bit) (16-bit) (256 bytes)
pic18f2220/2320/4220/4320 ds39599c-page 10 ? 2003 microchip technology inc. figure 1-2: pic18f4220/4320 block diagram instruction decode & control note 1: optional multiplexing of ccp2 input/output with rb3 is enabled by selection of the ccp2mx configuration bit. 2: re3 is available only when the mclr resets are disabled. 3: osc1, osc2, clki and clko are only available in select oscillator modes and when these pins are not being used as digital i/o. refer to section 2.0 ?oscillator configurations? for additional information. addressable enhanced synchronous timer0 timer1 timer2 serial port converter data latch data ram address latch address<12> 12 (2) bsr fsr0 fsr1 fsr2 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply wreg 8 bit op 8 8 alu<8> 8 address latch program memory (8 kbytes) data latch 20 21 21 16 8 8 8 inc/dec logic 21 8 data bus<8> 8 instruction 12 3 rom latch timer3 ccp2 bank0, f pclatu pcu usart master 8 register table latch ta b l e p o i n t e r < 2 > inc/dec logic data eeprom decode 10-bit a/d re3 (2) portd porte re0/an5/rd re1/an6/wr re2/an7/cs rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5/p1b rd6/psp6/p1c rd7/psp7/p1d power-up timer power-on reset watchdog timer v dd , v ss brown-out reset precision reference voltage low-voltage programming in-circuit debugger oscillator start-up timer osc1 (3) osc2 (3) t1osi t1oso fail-safe clock monitor porta portb portc ra4/t0cki/c1out ra5/an4/ss /lvdin/c2out rc0/t1oso/t1cki rc1/t1osi/ccp2 (1) rc2/ccp1/p1a rc3/sck/scl rc4/sdi/sda rc5/sdo rc6/tx/ck rc7/rx/dt ra3/an3/v ref + ra2/an2/v ref -/cv ref ra1/an1 ra0/an0 osc2/clko/ra6 (3) rb0/an12/int0 rb4/an11/kbi0 rb1/an10/int1 rb2/an8/int2 rb3/an9/ccp2 (1) rb5/kbi1/pgm rb6/kbi2/pgc rb7/kbi3/pgd osc1/clki/ra7 (3) ccp 8 mclr (2) internal int rc oscillator oscillator block (8- or 16-bit) (16-bit) (8-bit) (16-bit) (256 bytes) (512 bytes)
? 2003 microchip technology inc. ds39599c-page 11 pic18f2220/2320/4220/4320 table 1-2: pic18f2220/2320 pinout i/o descriptions pin name pin number pin type buffer type description pdip soic mclr /v pp /re3 mclr v pp re3 11 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 99 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 10 10 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 22 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 33 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 44 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. comparator reference voltage output. ra3/an3/v ref + ra3 an3 v ref + 55 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 66 i/o i o st/od st ? digital i/o. open-drain when configured as output. timer0 external clock input. comparator 1 output. ra5/an4/ss /lvdin/c2out ra5 an4 ss lvdin c2out 77 i/o i i i o ttl analog ttl analog ? digital i/o. analog input 4. spi slave select input. low-voltage detect input. comparator 2 output. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
pic18f2220/2320/4220/4320 ds39599c-page 12 ? 2003 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/an12/int0 rb0 an12 int0 21 21 i/o i i ttl analog st digital i/o. analog input 12. external interrupt 0. rb1/an10/int1 rb1 an10 int1 22 22 i/o i i ttl analog st digital i/o. analog input 10. external interrupt 1. rb2/an8/int2 rb2 an8 int2 23 23 i/o i i ttl analog st digital i/o. analog input 8. external interrupt 2. rb3/an9/ccp2 rb3 an9 ccp2 (1) 24 24 i/o i i/o ttl analog st digital i/o. analog input 9. capture2 input, compare2 output, pwm2 output. rb4/an11/kbi0 rb4 an11 kbi0 25 25 i/o i i ttl analog ttl digital i/o. analog input 11. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 26 26 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 27 27 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 28 28 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f2220/2320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip soic legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
? 2003 microchip technology inc. ds39599c-page 13 pic18f2220/2320/4220/4320 portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 11 11 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 12 12 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1/p1a rc2 ccp1 p1a 13 13 i/o i/o o st st ? digital i/o. capture1 input/compare1 output/pwm1 output. enhanced ccp1 output. rc3/sck/scl rc3 sck scl 14 14 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 15 15 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 16 16 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 17 17 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 18 18 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data (see related tx/ck). re3 ? ? ? ? see mclr /v pp /re3 pin. v ss 8, 19 8, 19 p ? ground reference for logic and i/o pins. v dd 20 20 p ? positive supply for logic and i/o pins. table 1-2: pic18f2220/2320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip soic legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
pic18f2220/2320/4220/4320 ds39599c-page 14 ? 2003 microchip technology inc. table 1-3: pic18f4220/4320 pinout i/o descriptions pin name pin number pin type buffer type description pdip tqfp qfn mclr /v pp /re3 mclr v pp re3 11818 i p i st st master clear (input) or programming voltage (input). master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. digital input. osc1/clki/ra7 osc1 clki ra7 13 30 32 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 14 31 33 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. porta is a bidirectional i/o port. ra0/an0 ra0 an0 21919 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 32020 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref -/cv ref ra2 an2 v ref - cv ref 42121 i/o i i o ttl analog analog analog digital i/o. analog input 2. a/d reference voltage (low) input. comparator reference voltage output. ra3/an3/v ref + ra3 an3 v ref + 52222 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki/c1out ra4 t0cki c1out 62323 i/o i o st/od st ? digital i/o. open-drain when configured as output. timer0 external clock input. comparator 1 output. ra5/an4/ss /lvdin/ c2out ra5 an4 ss lvdin c2out 72424 i/o i i i o ttl analog ttl analog ? digital i/o. analog input 4. spi slave select input. low-voltage detect input. comparator 2 output. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
? 2003 microchip technology inc. ds39599c-page 15 pic18f2220/2320/4220/4320 portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/an12/int0 rb0 an12 int0 33 8 9 i/o i i ttl analog st digital i/o. analog input 12. external interrupt 0. rb1/an10/int1 rb1 an10 int1 34 9 10 i/o i i ttl analog st digital i/o. analog input 10. external interrupt 1. rb2/an8/int2 rb2 an8 int2 35 10 11 i/o i i ttl analog st digital i/o. analog input 8. external interrupt 2. rb3/an9/ccp2 rb3 an9 ccp2 (1) 36 11 12 i/o i i/o ttl analog st digital i/o. analog input 9. capture2 input, compare2 output, pwm2 output. rb4/an11/kbi0 rb4 an11 kbi0 37 14 14 i/o i i ttl analog ttl digital i/o. analog input 11. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 38 15 15 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 39 16 16 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 40 17 17 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f4220/4320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip tqfp qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
pic18f2220/2320/4220/4320 ds39599c-page 16 ? 2003 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t1cki rc0 t1oso t1cki 15 32 34 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/ccp2 rc1 t1osi ccp2 (2) 16 35 35 i/o i i/o st cmos st digital i/o. timer1 oscillator input. capture2 input, compare2 output, pwm2 output. rc2/ccp1/p1a rc2 ccp1 p1a 17 36 36 i/o i/o o st st ? digital i/o. capture1 input/compare1 output/pwm1 output. enhanced ccp1 output. rc3/sck/scl rc3 sck scl 18 37 37 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rc4/sdi/sda rc4 sdi sda 23 42 42 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo rc5 sdo 24 43 43 i/o o st ? digital i/o. spi data out. rc6/tx/ck rc6 tx ck 25 44 44 i/o o i/o st ? st digital i/o. usart asynchronous transmit. usart synchronous clock (see related rx/dt). rc7/rx/dt rc7 rx dt 26 1 1 i/o i i/o st st st digital i/o. usart asynchronous receive. usart synchronous data (see related tx/ck). table 1-3: pic18f4220/4320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip tqfp qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
? 2003 microchip technology inc. ds39599c-page 17 pic18f2220/2320/4220/4320 portd is a bidirectional i/o port or a parallel slave port (psp) for interfacing to a microprocessor port. these pins have ttl input buffers when psp module is enabled. rd0/psp0 rd0 psp0 19 38 38 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 20 39 39 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 21 40 40 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 22 41 41 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4 rd4 psp4 27 2 2 i/o i/o st ttl digital i/o. parallel slave port data. rd5/psp5/p1b rd5 psp5 p1b 28 3 3 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. rd6/psp6/p1c rd6 psp6 p1c 29 4 4 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. rd7/psp7/p1d rd7 psp7 p1d 30 5 5 i/o i/o o st ttl ? digital i/o. parallel slave port data. enhanced ccp1 output. table 1-3: pic18f4220/4320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip tqfp qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
pic18f2220/2320/4220/4320 ds39599c-page 18 ? 2003 microchip technology inc. porte is a bidirectional i/o port. re0/an5/rd re0 an5 rd 82525 i/o i i st analog ttl digital i/o. analog input 5. read control for parallel slave port (see also wr and cs pins). re1/an6/wr re1 an6 wr 92626 i/o i i st analog ttl digital i/o. analog input 6. write control for parallel slave port (see cs and rd pins). re2/an7/cs re2 an7 cs 10 27 27 i/o i i st analog ttl digital i/o. analog input 7. chip select control for parallel slave port (see related rd and wr ). re3 1 18 18 ? ? see mclr /v pp /re3 pin. v ss 12, 31 6, 29 6, 30, 31 p ? ground reference for logic and i/o pins. v dd 11, 32 7, 28 7, 8, 28, 29 p ? positive supply for logic and i/o pins. nc ? ? 13 nc nc no connect. table 1-3: pic18f4220/4320 pinout i/o descriptions (continued) pin name pin number pin type buffer type description pdip tqfp qfn legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels i = input o = output p = power od = open-drain (no diode to v dd ) note 1: default assignment for ccp2 when ccp2mx (config3h<0>) is set. 2: alternate assignment for ccp2 when ccp2mx is cleared.
? 2003 microchip technology inc. ds39599c-page 19 pic18f2220/2320/4220/4320 2.0 oscillator configurations 2.1 oscillator types the pic18f2x20 and pic18f4x20 devices can be operated in ten different oscillator modes. the user can program the configuration bits, f osc 3:f osc 0, in configuration register 1h to select one of these ten modes: 1. lp low-power crystal 2. xt crystal/resonator 3. hs high-speed crystal/resonator 4. hspll high-speed crystal/resonator with pll enabled 5. rc external resistor/capacitor with f osc /4 output on ra6 6. rcio external resistor/capacitor with i/o on ra6 7. intio1 internal oscillator with f osc /4 output on ra6 and i/o on ra7 8. intio2 internal oscillator with i/o on ra6 and ra7 9. ec external clock with f osc /4 output 10. ecio external clock with i/o on ra6 2.2 crystal oscillator/ceramic resonators in xt, lp, hs or hspll oscillator modes, a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation. figure 2-1 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. figure 2-1: crystal/ceramic resonator operation (xt, lp, hs or hspll configuration) table 2-1: capacitor selection for ceramic resonators note: use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. typical capacitor values used: mode freq osc1 osc2 xt 455 khz 2.0 mhz 4.0 mhz 56 pf 47 pf 33 pf 56 pf 47 pf 33 pf hs 8.0 mhz 16.0 mhz 27 pf 22 pf 27 pf 22 pf capacitor values are for design guidance only. these capacitors were tested with the resonators listed below for basic start-up and operation. these values are not optimized . different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes on page 20 for additional information. resonators used: 455 khz 4.0 mhz 2.0 mhz 8.0 mhz 16.0 mhz note 1: see table 2-1 and table 2-2 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the oscillator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxxxx r s (2) internal
pic18f2220/2320/4220/4320 ds39599c-page 20 ? 2003 microchip technology inc. table 2-2: capacitor selection for crystal oscillator an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-2. figure 2-2: external clock input operation (hs osc configuration) 2.3 hspll a phase locked loop (pll) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. this may be useful for customers who are concerned with emi due to high-frequency crystals. the hspll mode makes use of the hs mode oscillator for frequencies up to 10 mhz. a pll then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 mhz. the pll is enabled only when the oscillator configura- tion bits are programmed for hspll mode. if programmed for any other mode, the pll is not enabled. figure 2-3: pll block diagram osc type crystal freq typical capacitor values tested: c1 c2 lp 32 khz 33 pf 33 pf 200 khz 15 pf 15 pf xt 1 mhz 33 pf 33 pf 4 mhz 27 pf 27 pf hs 4 mhz 27 pf 27 pf 8 mhz 22 pf 22 pf 20 mhz 15 pf 15 pf capacitor values are for design guidance only. these capacitors were tested with the crystals listed below for basic start-up and operation. these values are not optimized. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. see the notes following this table for additional information. crystals used: 32 khz 4 mhz 200 khz 8 mhz 1 mhz 20 mhz note 1: higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: when operating below 3v v dd , or when using certain ceramic resonators at any voltage, it may be necessary to use the hs mode or switch to a crystal oscillator. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: r s may be required to avoid overdriving crystals with low drive level specification. 5: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc1 osc2 open clock from ext. system pic18fxxxx (hs mode) mux vco loop filter crystal osc osc2 osc1 pll enable f in f out sysclk phase comparator hs osc enable 4 (from configuration register 1h) hs mode
? 2003 microchip technology inc. ds39599c-page 21 pic18f2220/2320/4220/4320 2.4 external clock input the ec and ecio oscillator modes require an external clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-4 shows the pin connections for the ec oscillator mode. figure 2-4: external clock input operation (ec configuration) the ecio oscillator mode functions like the ec mode, except that the osc2 pin becomes an additional gen- eral purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-5 shows the pin connections for the ecio oscillator mode. figure 2-5: external clock input operation (ecio configuration) 2.5 rc oscillator for timing insensitive applications, the ?rc? and ?rcio? device options offer additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) val- ues and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. furthermore, the dif- ference in lead frame capacitance between package types will also affect the oscillation frequency, espe- cially for low c ext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 2-6 shows how the r/c combination is connected. in the rc oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-6: rc oscillator mode the rcio oscillator mode (figure 2-7) functions like the rc mode, except that the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 6 of porta (ra6). figure 2-7: rcio oscillator mode osc1/clki osc2/clko f osc /4 clock from ext. system pic18fxxxx osc1/clki i/o (osc2) ra6 clock from ext. system pic18fxxxx osc2/clko c ext r ext pic18fxxxx osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf c ext r ext pic18fxxxx osc1 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? c ext > 20 pf i/o (osc2) ra6
pic18f2220/2320/4220/4320 ds39599c-page 22 ? 2003 microchip technology inc. 2.6 internal oscillator block the pic18f2x20/4x20 devices include an internal oscillator block which generates two different clock sig- nals. either can be used as the system?s clock source. this can eliminate the need for external oscillator circuits on the osc1 and/or osc2 pins. the main output (intosc) is an 8 mhz clock source which can be used to directly drive the system clock. it also drives a postscaler which can provide a range of clock frequencies from 125 khz to 4 mhz. the intosc output is enabled when a system clock frequency from 125 khz to 8 mhz is selected. the other clock source is the internal rc oscillator (intrc) which provides a 31 khz output. the intrc oscillator is enabled by selecting the internal oscillator block as the system clock source or when any of the following are enabled: power-up timer fail-safe clock monitor watchdog timer two-speed start-up these features are discussed in greater detail in section 23.0 ?special features of the cpu? . the clock source frequency (intosc direct, intrc direct or intosc postscaler) is selected by configuring the ircf bits of the osccon register (page 26). 2.6.1 intio modes using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins which can then be used for digital i/o. two distinct configurations are available: in intio1 mode, the osc2 pin outputs f osc /4, while osc1 functions as ra7 for digital input and output. in intio2 mode, osc1 functions as ra7 and osc2 functions as ra6, both for digital input and output. 2.6.2 intrc output frequency the internal oscillator block is calibrated at the factory to produce an intosc output frequency of 8.0 mhz. this changes the frequency of the intrc source from its nominal 31.25 khz. peripherals and features that depend on the intrc source will be affected by this shift in frequency. once set during factory calibration, the intrc frequency will remain within 1% as temperature and v dd change across their full specified operating ranges. 2.6.3 osctune register the internal oscillator?s output has been calibrated at the factory but can be adjusted in the user's application. this is done by writing to the osctune register (register 2-1). the tuning sensitivity is constant throughout the tuning range. when the osctune register is modified, the intosc and intrc frequencies will begin shifting to the new frequency. the intrc clock will reach the new fre- quency within 8 clock cycles (approximately 8*32 s = 256 s). the intosc clock will stabilize within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. oper- ation of features that depend on the intrc clock source frequency, such as the wdt, fail-safe clock monitor and peripherals, will also be affected by the change in frequency.
? 2003 microchip technology inc. ds39599c-page 23 pic18f2220/2320/4220/4320 register 2-1: osctune: oscillator tuning register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun5 tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frequency tuning bits 011111 = maximum frequency (+12.5%, approximately) 000001 000000 = center frequency. oscillator module is running at the calibrated frequency. 111111 100000 = minimum frequency (-12.5%, approximately) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 24 ? 2003 microchip technology inc. 2.7 clock sources and oscillator switching like previous pic18 devices, the pic18f2x20 and pic18f4x20 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. pic18f2x20/4x20 devices offer two alternate clock sources. when enabled, these give additional options for switching to the various power managed operating modes. essentially, there are three clock sources for these devices: primary oscillators secondary oscillators internal oscillator block the primary oscillators include the external crystal and resonator modes, the external rc modes, the external clock modes and the internal oscillator block. the particular mode is defined on por by the contents of configuration register 1h. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power managed mode. pic18f2x20/4x20 devices offer only the timer1 oscillator as a secondary oscillator. this oscillator, in all power managed modes, is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rc0/t1oso/t1cki and rc1/t1osi pins. like the lp mode oscillator circuit, loading capacitors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 12.2 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator block is available as a power managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the clock sources for the pic18f2x20/4x20 devices are shown in figure 2-8. see section 12.0 ?timer1 module? for further details of the timer1 oscillator. see section 23.1 ?configuration bits? for configuration register details. 2.7.1 oscillator control register the osccon register (register 2-2) controls several aspects of the system clock?s operation, both in full power operation and in power managed modes. the system clock select bits, scs1:scs0, select the clock source that is used when the device is operating in power managed modes. the available clock sources are the primary clock (defined in configuration register 1h), the secondary clock (timer1 oscillator) and the internal oscillator block. the clock selection has no effect until a sleep instruction is executed and the device enters a power managed mode of operation. the scs bits are cleared on all forms of reset. the internal oscillator select bits, ircf2:ircf0, select the frequency output of the internal oscillator block that is used to drive the system clock. the choices are the intrc source, the intosc source (8 mhz) or one of the six frequencies derived from the intosc postscaler (125 khz to 4 mhz). if the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator?s output. the osts, iofs and t1run bits indicate which clock source is currently providing the system clock. the osts indicates that the oscillator start-up timer has timed out and the primary clock is providing the system clock in primary clock modes. the iofs bit indicates when the internal oscillator block has stabilized and is providing the system clock in rc clock modes. the t1run bit (t1con<6>) indicates when the timer1 oscillator is providing the system clock in secondary clock modes. if none of these bits are set, the intrc is providing the system clock, or the internal oscillator block has just started and is not yet stable. the idlen bit controls the selective shutdown of the controller?s cpu in power managed modes. the use of these bits is discussed in more detail in section 3.0 ?power managed modes? . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to set the scs0 bit will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before executing the sleep instruction or a very long delay may occur while the timer1 oscillator starts.
? 2003 microchip technology inc. ds39599c-page 25 pic18f2220/2320/4220/4320 figure 2-8: pic18f2x20/4x20 clock diagram pic18f2x20/4x20 4 x pll config1h <3:0> secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep primary oscillator hspll lp, xt, hs, rc, ec t1osc cpu peripherals idlen postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz osccon<6:4> 111 110 101 100 011 010 001 000 31 khz intrc source internal oscillator block wdt, fscm 8 mhz internal oscillator (intosc) osccon<6:4> clock control osccon<1:0>
pic18f2220/2320/4220/4320 ds39599c-page 26 ? 2003 microchip technology inc. register 2-2: osccon register r/w-0 r/w-0 r/w-0 r/w-0 r (1) r-0 r/w-0 r/w-0 idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 bit 7 bit 0 bit 7 idlen: idle enable bit 1 = idle mode enabled; cpu core is not clocked in power managed modes 0 = run mode enabled; cpu core is clocked in power managed modes bit 6-4 ircf2:ircf0: internal oscillator frequency select bits 111 = 8 mhz (8 mhz source drives clock directly) 110 = 4 mhz 101 = 2 mhz 100 = 1 mhz 011 = 500 khz 010 = 250 khz 001 = 125 khz 000 = 31 khz (intrc source drives clock directly) bit 3 osts: oscillator start-up time-out status bit (1) 1 = oscillator start-up time-out timer ha s expired; primary oscillator is running 0 = oscillator start-up time-out timer is running; primary oscillator is not ready bit 2 iofs: intosc frequency stable bit 1 = intosc frequency is stable 0 = intosc frequency is not stable bit 1-0 scs1:scs0: system clock select bits 1x = internal oscillator block (rc modes) 01 = timer1 oscillator (secondary modes) (2) 00 = primary oscillator (sleep and pri_idle modes) note 1: depends on state of ieso bit in configuration register 1h. 2: scs0 may not be set while t1oscen (t1con<3>) is clear. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 27 pic18f2220/2320/4220/4320 2.7.2 oscillator transitions the pic18f2x20/4x20 devices contain circuitry to pre- vent clocking ?glitches? when switching between clock sources. a short pause in the system clock occurs dur- ing the clock switch. the length of this pause is between 8 and 9 clock periods of the new clock source. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. clock transitions are discussed in greater detail in section 3.1.2 ?entering power managed modes? . 2.8 effects of power managed modes on the various clock sources when the device executes a sleep instruction, the system is switched to one of the power managed modes, depending on the state of the idlen and scs1:scs0 bits of the osccon register. see section 3.0 ?power managed modes? for details. when pri_idle mode is selected, the designated pri- mary oscillator continues to run without interruption. for all other power managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin, if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and pro- viding the system clock. the timer1 oscillator may also run in all power managed modes if required to clock timer1 or timer3. in internal oscillator modes (rc_run and rc_idle), the internal oscillator block provides the system clock source. the intrc output can be used directly to provide the system clock and may be enabled to support various special features, regardless of the power managed mode (see section 23.2 ?watchdog timer (wdt)? through section 23.4 ?fail-safe clock monitor? ). the intosc output at 8 mhz may be used directly to clock the system or may be divided down first. the intosc output is disabled if the system clock is provided directly from the intrc output. if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real- time clock. other features may be operating that do not require a system clock source (i.e., ssp slave, psp, intn pins, a/d conversions and others). 2.9 power-up delays power-up delays are controlled by two timers so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply is stable under nor- mal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see section 4.1 ?power-on reset (por)? through section 4.5 ?brown-out reset (bor)? . the first timer is the power-up timer (pwrt) which provides a fixed delay on power-up (parameter 33, table 26-10), if enabled, in configuration register 2l. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crys- tal oscillator is stable (lp, xt and hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. when the hspll oscillator mode is selected, the device is kept in reset for an additional 2 ms, following the hs mode ost delay, so the pll can lock to the incoming clock frequency. there is a delay of 5 to 10 s, following por, while the controller becomes ready to execute instructions. this delay runs concurrently with any other delays. this may be the only delay that occurs when any of the ec, rc or intio modes are used as the primary clock source. table 2-3: osc1 and osc2 pin states in sleep mode osc mode osc1 pin osc2 pin rc, intio1 floating, external resistor should pull high at logic low (clock/4 output) rcio, intio2 floating, external resistor should pull high configured as porta, bit 6 ecio floating, pulled by external clock configured as porta, bit 6 ec floating, pulled by external clock at logic low (clock/4 output) lp, xt, and hs feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 4-1 in section 4.0 ?reset? for time-outs due to sleep and mclr reset.
pic18f2220/2320/4220/4320 ds39599c-page 28 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 29 pic18f2220/2320/4220/4320 3.0 power managed modes the pic18f2x20 and pic18f4x20 devices offer a total of six operating modes for more efficient power management (see table 3-1). these operating modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). there are three categories of power managed modes: sleep mode idle modes run modes these categories define which portions of the device are clocked and sometimes, what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or intosc multiplexer); the sleep mode does not use a clock source. the clock switching feature offered in other pic18 devices (i.e., using the timer1 oscillator in place of the primary oscillator) and the sleep mode offered by all picmicro ? devices (where all system clocks are stopped) are both offered in the pic18f2x20/4x20 devices (sec_run and sleep modes, respectively). however, additional power managed modes are avail- able that allow the user greater flexibility in determining what portions of the device are operating. the power managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. for pic18f2x20/4x20 devices, the power managed modes are invoked by using the existing sleep instruction. all modes exit to pri_run mode when trig- gered by an interrupt, a reset, or a wdt time-out (pri_run mode is the normal full power execution mode; the cpu and peripherals are clocked by the pri- mary oscillator source). in addition, power managed run modes may also exit to sleep mode or their corresponding idle mode. 3.1 selecting power managed modes selecting a power managed mode requires deciding if the cpu is to be clocked or not and selecting a clock source. the idlen bit controls cpu clocking while the sc1:scs0 bits select a clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 3-1. 3.1.1 clock sources the clock source is selected by setting the scs bits of the osccon register. three clock sources are avail- able for use in power managed idle modes: the primary clock (as configured in configuration register 1h), the secondary clock (timer1 oscillator) and the internal oscillator block. the secondary and internal oscillator block sources are available for the power managed modes (pri_run mode is the normal full power exe- cution mode; the cpu and peripherals are clocked by the primary oscillator source). table 3-1: power managed modes mode osccon bits module clocking available clock and oscillator source idlen <7> scs1:scs0 <1:0> cpu peripherals sleep 000 off off none ? all clocks are disabled pri_run 000 clocked clocked primary ? lp, xt, hs, hspll, rc, ec, intrc (1) . this is the normal full power execution mode. sec_run 001 clocked clocked secondary ? timer1 oscillator rc_run 01x clocked clocked internal oscillator block (1) pri_idle 100 off clocked primary ? lp, xt, hs, hspll, rc, ec sec_idle 101 off clocked secondary ? timer1 oscillator rc_idle 11x off clocked internal oscillator block (1) note 1: includes intosc and intosc postsc aler, as well as the intrc source.
pic18f2220/2320/4220/4320 ds39599c-page 30 ? 2003 microchip technology inc. 3.1.2 entering power managed modes in general, entry, exit and switching between power managed clock sources requires clock source switching. in each case, the sequence of events is the same. any change in the power managed mode begins with loading the osccon register and executing a sleep instruction. the scs1:scs0 bits select one of three power managed clock sources; the primary clock (as defined in configuration register 1h), the secondary clock (the timer1 oscillator) and the internal oscillator block (used in rc modes). modifying the scs bits will have no effect until a sleep instruction is executed. entry to the power managed mode is triggered by the execution of a sleep instruction. figure 3-5 shows how the system is clocked while switching from the primary clock to the timer1 oscilla- tor. when the sleep instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. eight clock cycles from the new clock source are counted to synchronize with the new clock source. after eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. the actual length of the pause is between eight and nine clock periods from the new clock source. this ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. three bits indicate the current clock source: osts and iofs in the osccon register and t1run in the t1con register. only one of these bits will be set while in a power managed mode other than pri_run. when the osts bit is set, the primary clock is providing the system clock. when the iofs bit is set, the intosc output is providing a stable 8 mhz clock source and is providing the system clock. when the t1run bit is set, the timer1 oscillator is providing the system clock. if none of these bits are set, then either the intrc clock source is clocking the system or the intosc source is not yet stable. if the internal oscillator block is configured as the pri- mary clock source in configuration register 1h, then both the osts and iofs bits may be set when in pri_run or pri_idle modes. this indicates that the primary clock (intosc output) is generating a stable 8 mhz output. entering a power managed rc mode (same frequency) would clear the osts bit. 3.1.3 multiple sleep commands the power managed mode that is invoked with the sleep instruction is determined by the settings of the idlen and scs bits at the time the instruction is exe- cuted. if another sleep instruction is executed, the device will enter the power managed mode specified by these same bits at that time. if the bits have changed, the device will enter the new power managed mode specified by the new bit settings. 3.1.4 comparisons between run and idle modes clock source selection for the run modes is identical to the corresponding idle modes. when a sleep instruc- tion is executed, the scs bits in the osccon register are used to switch to a different clock source. as a result, if there is a change of clock source at the time a sleep instruction is executed, a clock switch will occur. in idle modes, the cpu is not clocked and is not run- ning. in run modes, the cpu is clocked and executing code. this difference modifies the operation of the wdt when it times out. in idle modes, a wdt time-out results in a wake from power managed modes. in run modes, a wdt time-out results in a wdt reset (see table 3-2). during a wake-up from an idle mode, the cpu starts executing code by entering the corresponding run mode until the primary clock becomes ready. when the primary clock becomes ready, the clock source is auto- matically switched to the primary clock. the idlen and scs bits are unchanged during and after the wake-up. figure 3-2 shows how the system is clocked during the clock source switch. the example assumes the device was in sec_idle or sec_run mode when a wake is triggered (the primary clock was configured in hspll mode). note 1: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. 2: executing a sleep instruction does not necessarily place the device into sleep mode; executing a sleep instruction is simply a trigger to place the controller into a power managed mode selected by the osccon register, one of which is sleep mode.
? 2003 microchip technology inc. ds39599c-page 31 pic18f2220/2320/4220/4320 3.2 sleep mode the power managed sleep mode in the pic18f2x20/ 4x20 devices is identical to that offered in all other picmicro controllers. it is entered by clearing the idlen and scs1:scs0 bits (this is the reset state) and executing the sleep instruction. this shuts down the primary oscillator and the osts bit is cleared (see figure 3-1). when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the system will not be clocked until the primary clock source becomes ready (see figure 3-2), or it will be clocked from the internal oscillator block if either the two-speed start-up or the fail-safe clock monitor are enabled (see section 23.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the system clocks. the idlen and scs bits are not affected by the wake-up. 3.3 idle modes the idlen bit allows the controller?s cpu to be selectively shut down while the peripherals continue to operate. clearing idlen allows the cpu to be clocked. setting idlen disables clocks to the cpu, effectively stopping program execution (see register 2-2). the peripherals continue to be clocked regardless of the setting of the idlen bit. there is one exception to how the idlen bit functions. when all the low-power osccon bits are cleared (idlen:scs1:scs0 = 000 ), the device enters sleep mode upon the execution of the sleep instruction. this is both the reset state of the osccon register and the setting that selects sleep mode. this maintains com- patibility with other picmicro devices that do not offer power managed modes. if the idle enable bit, idlen (osccon<7>), is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake-up event occurs, cpu execution is delayed approximately 10 s while it becomes ready to execute code. when the cpu begins executing code, it is clocked by the same clock source as was selected in the power managed mode (i.e., when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals until the primary clock source becomes ready ? this is essentially rc_run mode). this continues until the primary clock source becomes ready. when the primary clock becomes ready, the osts bit is set and the system clock source is switched to the primary clock (see figure 3-4). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to full power operation. table 3-2: comparison between power managed modes power managed mode cpu is clocked by ... wdt time-out causes a ... peripherals are clocked by ... clock during wake-up (while primary becomes ready) sleep not clocked (not running) wake-up not clocked none or intosc multiplexer if two-speed start-up or fail-safe clock monitor are enabled. any idle mode not clocked (not running) wake-up primary, secondary or intosc multiplexer unchanged from idle mode (cpu operates as in corresponding run mode). any run mode secondary or intosc multiplexer reset secondary or intosc multiplexer unchanged from run mode.
pic18f2220/2320/4220/4320 ds39599c-page 32 ? 2003 microchip technology inc. figure 3-1: timing transition for entry to sleep mode figure 3-2: transition timing for wake from sleep (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 8 pc + 6 q1 q2 q3 q4 wake-up event note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 4 pc + 2
? 2003 microchip technology inc. ds39599c-page 33 pic18f2220/2320/4220/4320 3.3.1 pri_idle mode this mode is unique among the three low-power idle modes in that it does not disable the primary system clock. for timing sensitive applications, this allows for the fastest resumption of device operation, with its more accurate primary clock source, since the clock source does not have to ?warm up? or transition from another oscillator. pri_idle mode is entered by setting the idlen bit, clearing the scs bits and executing a sleep instruc- tion. although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified in configuration register 1h. the osts bit remains set in pri_idle mode (see figure 3-3). when a wake-up event occurs, the cpu is clocked from the primary clock source. a delay of approxi- mately 10 s is required between the wake-up event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-4). figure 3-3: transition timing to pri_idle mode figure 3-4: transition timing for wake from pri_idle mode q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock pc + 2 q1 q3 q4 clock counter q2 wake-up event cpu start-up delay
pic18f2220/2320/4220/4320 ds39599c-page 34 ? 2003 microchip technology inc. 3.3.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered by setting the idlen bit, modifying to scs1:scs0 = 01 and executing a sleep instruction. when the clock source is switched to the timer1 oscillator (see figure 3-5), the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake-up event occurs, the peripherals continue to be clocked from the timer1 oscillator. after a 10 s delay following the wake-up event, the cpu begins exe- cuting code, being clocked by the timer1 oscillator. the microcontroller operates in sec_run mode until the primary clock becomes ready. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-6). when the clock switch is com- plete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. figure 3-5: timing transition for entry to sec_idle mode figure 3-6: timing transition for wake from sec_run mode (hspll) note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when try- ing to set the scs0 bit (osccon<0>), the write to scs0 will not occur. if the timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started; in such sit- uations, initial oscillator operation is far from stable and unpredictable operation may result. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q1 q3 q4 osc1 peripheral program pc pc + 2 t1osi pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake-up from interrupt event t ost (1) t pll (1) 12345678 clock transition osts bit set
? 2003 microchip technology inc. ds39599c-page 35 pic18f2220/2320/4220/4320 3.3.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator block using the intosc multiplexer. this mode allows for controllable power conservation during idle periods. this mode is entered by setting the idlen bit, setting scs1 (scs0 is ignored) and executing a sleep instruction. the intosc multiplexer may be used to select a higher clock frequency by modifying the ircf bits before executing the sleep instruction. when the clock source is switched to the intosc multiplexer (see figure 3-7), the primary oscillator is shut down and the osts bit is cleared. if the ircf bits are set to a non-zero value (thus enabling the intosc output), the iofs bit becomes set after the intosc output becomes stable, in about 1 ms. clocks to the peripherals continue while the intosc source stabilizes. if the ircf bits were previ- ously at a non-zero value before the sleep instruction was executed and the intosc source was already stable, the iofs bit will remain set. if the ircf bits are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. when a wake-up event occurs, the peripherals con- tinue to be clocked from the intosc multiplexer. after a 10 s delay following the wake-up event, the cpu begins executing code, being clocked by the intosc multiplexer. the microcontroller operates in rc_run mode until the primary clock becomes ready. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-8). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-7: timing transition to rc_idle mode figure 3-8: timing transition for wake from rc_run mode (rc_run to pri_run) q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake-up from interrupt event t ost (1) t pll (1) 12345678 clock transition osts bit set multiplexer q4
pic18f2220/2320/4220/4320 ds39599c-page 36 ? 2003 microchip technology inc. 3.4 run modes if the idlen bit is clear when a sleep instruction is executed, the cpu and peripherals are both clocked from the source selected using the scs1:scs0 bits. while these operating modes may not afford the power conservation of idle or sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. rc_run mode also offers the possibility of executing code at a frequency greater than the primary clock. wake-up from a power managed run mode can be triggered by an interrupt, or any reset, to return to full power operation. as the cpu is executing code in run modes, several additional exits from run modes are possible. they include exit to sleep mode, exit to a cor- responding idle mode, and exit by executing a reset instruction. while the device is in any of the power managed run modes, a wdt time-out will result in a wdt reset. 3.4.1 pri_run mode the pri_run mode is the normal full power execution mode. if the sleep instruction is never executed, the microcontroller operates in this mode (a sleep instruc- tion is executed to enter all other power managed modes). all other power managed modes exit to pri_run mode when an interrupt or wdt time-out occur. there is no entry to pri_run mode. the osts bit is set. the iofs bit may be set if the internal oscillator block is the primary clock source (see section 2.7.1 ?oscillator control register? ). 3.4.2 sec_run mode the sec_run mode is the compatible mode to the ?clock switching? feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high accuracy clock source. sec_run mode is entered by clearing the idlen bit, setting scs1:scs0 = 01 and executing a sleep instruction. the system clock source is switched to the timer1 oscillator (see figure 3-9), the primary oscilla- tor is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. when a wake-up event occurs, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-6). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. firmware can force an exit from sec_run mode. by clearing the t1oscen bit (t1con<3>), an exit from sec_run back to normal full power operation is trig- gered. the timer1 oscillator will continue to run and provide the system clock even though the t1oscen bit is cleared. the primary clock is started. when the pri- mary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-6). when the clock switch is complete, the timer1 oscillator is disabled, the t1run bit is cleared, the osts bit is set and the pri- mary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. figure 3-9: timing transition for entry to sec_run mode note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when try- ing to set the scs0 bit, the write to scs0 will not occur. if the timer1 oscilla- tor is enabled, but not yet running, system clocks will be delayed until the oscillator has started; in such situations, initial oscil- lator operation is far from stable and unpredictable operation may result. q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 12345678 clock transition q4 q3 q2 q1 q3 q2 pc + 2
? 2003 microchip technology inc. ds39599c-page 37 pic18f2220/2320/4220/4320 3.4.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator block using the intosc multiplexer and the primary clock is shut down. when using the intrc source, this mode pro- vides the best power conservation of all the run modes while still executing code. it works well for user applica- tions which are not highly timing sensitive or do not require high-speed clocks at all times. if the primary clock source is the internal oscillator block (either of the intio1 or intio2 oscillators), there are no distinguishable differences between pri_run and rc_run modes during execution. however, a clock switch delay will occur during entry to, and exit from, rc_run mode. therefore, if the primary clock source is the internal oscillator block, the use of rc_run mode is not recommended. this mode is entered by clearing the idlen bit, setting scs1 (scs0 is ignored) and executing a sleep instruction. the ircf bits may select the clock frequency before the sleep instruction is executed. when the clock source is switched to the intosc multiplexer (see figure 3-10), the primary oscillator is shut down and the osts bit is cleared. the ircf bits may be modified at any time to immedi- ately change the system clock speed. executing a sleep instruction is not required to select a new clock frequency from the intosc multiplexer. if the ircf bits are all clear, the intosc output is not enabled and the iofs bit will remain clear; there will be no indication of the current clock source. the intrc source is providing the system clocks. if the ircf bits are changed from all clear (thus enabling the intosc output), the iofs bit becomes set after the intosc output becomes stable. clocks to the system continue while the intosc source stabilizes in approximately 1 ms. if the ircf bits were previously at a non-zero value before the sleep instruction was executed and the intosc source was already stable, the iofs bit will remain set. when a wake-up event occurs, the system continues to be clocked from the intosc multiplexer while the pri- mary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-8). when the clock switch is complete, the iofs bit is cleared, the osts bit is set and the primary clock is providing the system clock. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-10: timing transition to rc_run mode note: caution should be used when modifying a single ircf bit. if v dd is less than 3v, it is possible to select a higher clock speed than is supported by the low v dd . improper device operation may result if the v dd /f osc specifications are violated. q3 q2 q1 osc1 peripheral program q4 intrc q4 counter clock cpu clock pc + 2 pc 12345678 clock transition q3 q2 q1 q4 q2 q1 q3 pc + 4
pic18f2220/2320/4220/4320 ds39599c-page 38 ? 2003 microchip technology inc. 3.4.4 exit to idle mode an exit from a power managed run mode to its corre- sponding idle mode is executed by setting the idlen bit and executing a sleep instruction. the cpu is halted at the beginning of the instruction following the sleep instruction. there are no changes to any of the clock source status bits (osts, iofs or t1run). while the cpu is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.5 exit to sleep mode an exit from a power managed run mode to sleep mode is executed by clearing the idlen and scs1:scs0 bits and executing a sleep instruction. the code is no different than the method used to invoke sleep mode from the normal operating (full power) mode. the primary clock and internal oscillator block are dis- abled. the intrc will continue to operate if the wdt is enabled. the timer1 oscillator will continue to run, if enabled, in the t1con register. all clock source status bits are cleared (osts, iofs and t1run). 3.5 wake-up from power managed modes an exit from any of the power managed modes is trig- gered by an interrupt, a reset, or a wdt time-out. this section discusses the triggers that cause exits from power managed modes. the clocking subsystem actions are discussed in each of the power managed modes (see section 3.2 ?sleep mode? through section 3.4 ?run modes? ). device behavior during low-power mode exits is summarized in table 3-3. 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit a power managed mode and resume full power operation. to enable this functionality, an inter- rupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from lower power mode by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 ?interrupts? ). note: if application code is timing sensitive, it should wait for the osts bit to become set before continuing. use the interval during the low-power exit sequence (before osts is set) to perform timing insensitive ?housekeeping? tasks.
? 2003 microchip technology inc. ds39599c-page 39 pic18f2220/2320/4220/4320 table 3-3: activity and exit delay on wake-up from sleep mode or any idle mode (by clock sources) clock in power managed mode primary system clock power managed mode exit delay clock ready status bit (osccon) activity during wake-up from power managed mode exit by interrupt exit by reset primary system clock (pri_idle mode) lp, xt, hs 5-10 s (5) osts cpu and peripherals clocked by primary clock and executing instructions. not clocked or two-speed start-up (if enabled) (3) . hspll ec, rc, intrc (1) ? intosc (2) iofs t1osc or intrc (1) lp, xt, hs ost osts cpu and peripherals clocked by selected power managed mode clock and executing instructions until primary clock source becomes ready. hspll ost + 2 ms ec, rc, intrc (1) 5-10 s (5) ? intosc (2) 1ms (4) iofs intosc (2) lp, xt, hs ost osts hspll ost + 2 ms ec, rc, intrc (1) 5-10 s (5) ? intosc (2) none iofs sleep mode lp, xt, hs ost osts not clocked or two-speed start-up (if enabled) until primary clock source becomes ready (3) . hspll ost + 2 ms ec, rc, intrc (1) 5-10 s (5) ? intosc (2) 1ms (4) iofs note 1: in this instance, refers specifically to the intrc clock source. 2: includes both the intosc 8 mhz source and postscaler derived frequencies. 3: two-speed start-up is covered in greater detail in section 23.3 ?two-speed start-up? . 4: execution continues during the intosc stabilization period. 5: required delay when waking from sleep and all idle modes. this delay runs concurrently with any other required delays (see section 3.3 ?idle modes? ).
pic18f2220/2320/4220/4320 ds39599c-page 40 ? 2003 microchip technology inc. 3.5.2 exit by reset normally, the device is held in reset by the oscillator start-up timer (ost) until the primary clock (defined in configuration register 1h) becomes ready. at that time, the osts bit is set and the device begins executing code. code execution can begin before the primary clock becomes ready. if either the two-speed start-up (see section 23.3 ?two-speed start-up? ) or fail-safe clock monitor (see section 23.4 ?fail-safe clock monitor? ) are enabled in configuration register 1h, the device may begin execution as soon as the reset source has cleared. execution is clocked by the intosc multiplexer driven by the internal oscillator block. since the osccon register is cleared following all resets, the intrc clock source is selected. a higher speed clock may be selected by modifying the ircf bits in the osccon register. execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 3.5.3 exit by wdt time-out a wdt time-out will cause different actions depending on which power managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in a wake-up from the power managed mode (see section 3.2 ?sleep mode? through section 3.4 ?run modes? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 23.2 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by execut- ing a sleep or clrwdt instruction, the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) and modifying the ircf bits in the osccon register if the internal oscillator block is the system clock source. 3.5.4 exit without an oscillator start-up delay certain exits from power managed modes do not invoke the ost at all. these are: pri_idle mode, where the primary clock source is not stopped; and the primary clock source is not any of the lp, xt, hs or hspll modes. in these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (pri_idle), or normally does not require an oscillator start-up delay (rc, ec and intio oscillator modes). however, a fixed delay (approximately 10 s) following the wake-up event is required when leaving sleep and idle modes. this delay is required for the cpu to pre- pare for execution. instruction execution resumes on the first clock cycle following this delay. 3.6 intosc frequency drift the factory calibrates the internal oscillator block output (intosc) for 8 mhz. however, this frequency may drift as v dd or temperature changes, which can affect the controller operation in a variety of ways. it is possible to adjust the intosc frequency by modi- fying the value in the osctune register. this has the side effect that the intrc clock source frequency is also affected. however, the features that use the intrc source often do not require an exact frequency. these features include the fail-safe clock monitor, the watchdog timer and the rc_run/rc_idle modes when the intrc clock source is selected. being able to adjust the intosc requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. three examples are shown but other techniques may be used.
? 2003 microchip technology inc. ds39599c-page 41 pic18f2220/2320/4220/4320 3.6.1 example ? usart an adjustment may be indicated when the usart begins to generate framing errors or receives data with errors while in asynchronous mode. framing errors indicate that the system clock frequency is too high ? try decrementing the value in the osctune register to reduce the system clock frequency. errors in data may suggest that the system clock speed is too low ? increment osctune. 3.6.2 example ? timers this technique compares system clock speed to some reference clock. two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the timer1 oscillator. both timers are cleared but the timer clocked by the ref- erence generates interrupts. when an interrupt occurs, the internally clocked timer is read and both timers are cleared. if the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast ? decrement osctune. 3.6.3 example ? ccp in capture mode a ccp module can use free running timer1 (or timer3), clocked by the internal oscillator block and an external event with a known period (i.e., ac power fre- quency). the time of the first event is captured in the ccprxh:ccprxl registers and is recorded for use later. when the second event causes a capture, the time of the first event is subtracted from the time of the second event. since the period of the external event is known, the time difference between events can be calculated. if the measured time is much greater than the calculated time, the internal oscillator block is running too fast ? decrement osctune. if the measured time is much less than the calculated time, the internal oscillator block is running too slow ? increment osctune.
pic18f2220/2320/4220/4320 ds39599c-page 42 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 43 pic18f2220/2320/4220/4320 4.0 reset the pic18f2x20/4x20 devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset while executing instructions c) mclr reset when not executing instructions d) watchdog timer (wdt) reset (during execution) e) programmable brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up since this is viewed as the resumption of normal oper- ation. status bits from the rcon register, ri , to , pd , por and bor , are set or cleared differently in different reset situations as indicated in table 4-2. these bits are used in software to determine the nature of the reset. see table 4-3 for a full description of the reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. the enhanced mcu devices have a mclr noise filter in the mclr reset path. the filter will detect and ignore small pulses. the mclr pin is not driven low by any internal resets, including the wdt. the mclr input provided by the mclr pin can be dis- abled with the mclre bit in configuration register 3h (config3h<7>). see section 23.1 ?configuration bits? for more information. figure 4-1: simplified block diagram of on-chip reset circuit external reset mclr v dd osc1 wdt time-out v dd rise detect ost/pwrt intrc (1) por pulse ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter enable ost (2) enable pwrt note 1: this is the intrc source from the inte rnal oscillator block and is separate from the rc oscillator of the clki pin. 2: see table 4-1 for time-out situations. brown-out reset boren reset instruction stack pointer stack full/underflow reset sleep ( )_idle 1024 cycles 65.5 ms 32 s mclre s r q
pic18f2220/2320/4220/4320 ds39599c-page 44 ? 2003 microchip technology inc. 4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected. to take advantage of the por cir- cuitry, just tie the mclr pin through a resistor (1k to 10 k ? ) to v dd . this will eliminate external rc compo- nents usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 4-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (volt- age, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. figure 4-2: external power-on reset circuit (for slow v dd power-up) 4.2 power-up timer (pwrt) the power-up timer (pwrt) of the pic18f2x20/4x20 devices is an 11-bit counter, which uses the intrc source as the clock input. this yields a count of 2048 x 32 s = 65.6 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip-to-chip due to temperature and process variation. see dc parameter #33 for details. the pwrt is enabled by clearing configuration bit, pwrten . 4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over (parameter #33). this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp, hs and hspll modes and only on power-on reset, or on exit from most power managed modes. 4.4 pll lock time-out with the pll enabled in its pll mode, the time-out sequence following a power-on reset is slightly different from other oscillator modes. a portion of the power-up timer is used to provide a fixed time-out that is sufficient for the pll to lock to the main oscillator fre- quency. this pll lock time-out (t pll ) is typically 2 ms and follows the oscillator start-up time-out. 4.5 brown-out reset (bor) a configuration bit, boren, can disable (if clear/ programmed) or enable (if set) the brown-out reset cir- cuitry. if v dd falls below v bor (parameter d005) for greater than t bor (parameter #35), the brown-out situ- ation will reset the chip. a reset may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . if the power-up timer is enabled, it will be invoked after v dd rises above v bor ; it then will keep the chip in reset for an additional time delay t pwrt (parameter #33). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above v bor , the power-up timer will execute the additional time delay. enabling bor reset does not automatically enable the pwrt. 4.6 time-out sequence on power-up, the time-out sequence is as follows: first, after the por pulse has cleared, pwrt time-out is invoked (if enabled). then, the ost is activated. the total time-out will vary based on oscillator configuration and the status of the pwrt. for example, in rc mode with the pwrt disabled, there will be no time-out at all. figure 4-3, figure 4-4, figure 4-5, figure 4-6 and figure 4-7 depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, all time-outs will expire. bring- ing mclr high will begin execution immediately (figure 4-5). this is useful for testing purposes or to synchronize more than one pic18fxxxx device operating in parallel. table 4-2 shows the reset conditions for some special function registers, while table 4-3 shows the reset conditions for all the registers. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k ? is recommended to make sure that the voltage drop across r does not violate the device?s elec trical specification. 3: r1 1 k ? will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18fxxxx v dd
? 2003 microchip technology inc. ds39599c-page 45 pic18f2220/2320/4220/4320 table 4-1: time-out in various situations register 4-1: rcon register bits and positions table 4-2: status bits, their significanc e and the initialization condition for rcon register oscillator configuration power-up (2) and brown-out exit from power managed mode pwrten = 0 pwrten = 1 hspll 66 ms (1) + 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) 1024 t osc + 2 ms (2) hs, xt, lp 66 ms (1) + 1024 t osc 1024 t osc 1024 t osc ec, ecio 66 ms (1) ?? rc, rcio 66 ms (1) ?? intio1, intio2 66 ms (1) ?? note 1: 66 ms (65.5 ms) is the nominal power-up timer (pwrt) delay. 2: 2 ms is the nominal time required for the 4x pll to lock. r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-1 r/w-1 ipen ? ?ri to pd por bor bit 7 bit 0 note: refer to section 5.14 ?rcon register? for bit definitions. condition program counter rcon register ri to pd por bor stkful stkunf power-on reset 0000h 0--1 1100 1 1 1 0 0 0 0 reset instruction 0000h 0--0 uuuu 0 u u u u u u brown-out 0000h 0--1 11u- 1 1 1 u 0 u u mclr during power managed run modes 0000h 0--u 1uuu u 1 u u u u u mclr during power managed idle modes and sleep mode 0000h 0--u 10uu u 1 0 u u u u wdt time-out during full power or power managed run mode 0000h 0--u 0uuu u 0 u u u u u mclr during full power execution 0000h 0--u uuuu u u u u u uu stack full reset (stvren = 1 ) 1u stack underflow reset (stvren = 1 ) u1 stack underflow error (not an actual reset, stvren = 0 ) 0000h u--u uuuu u u u u u u 1 wdt time-out during power managed idle or sleep modes pc + 2 u--u 00uu u 0 0 u u u u interrupt exit from power managed modes pc + 2 u--u u0uu u u 0 u u u u legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ? note 1: when the wake-up is due to an interrupt and the gieh or giel bits are set, the pc is loaded with the interrupt vector (0x000008h or 0x000018h).
pic18f2220/2320/4220/4320 ds39599c-page 46 ? 2003 microchip technology inc. table 4-3: initialization co nditions for all registers register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt tosu 2220 2320 4220 4320 ---0 0000 ---0 0000 ---0 uuuu (3) tosh 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu (3) tosl 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu (3) stkptr 2220 2320 4220 4320 uu-0 0000 00-0 0000 uu-u uuuu (3) pclatu 2220 2320 4220 4320 ---0 0000 ---0 0000 ---u uuuu pclath 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu pcl 2220 2320 4220 4320 0000 0000 0000 0000 pc + 2 (2) tblptru 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu tblptrh 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu tblptrl 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu tablat 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu prodh 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu prodl 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu intcon 2220 2320 4220 4320 0000 000x 0000 000u uuuu uuuu (1) intcon2 2220 2320 4220 4320 1111 -1-1 1111 -1-1 uuuu -u-u (1) intcon3 2220 2320 4220 4320 11-0 0-00 11-0 0-00 uu-u u-uu (1) indf0 2220 2320 4220 4320 n/a n/a n/a postinc0 2220 2320 4220 4320 n/a n/a n/a postdec0 2220 2320 4220 4320 n/a n/a n/a preinc0 2220 2320 4220 4320 n/a n/a n/a plusw0 2220 2320 4220 4320 n/a n/a n/a fsr0h 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu fsr0l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu wreg 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu indf1 2220 2320 4220 4320 n/a n/a n/a postinc1 2220 2320 4220 4320 n/a n/a n/a postdec1 2220 2320 4220 4320 n/a n/a n/a preinc1 2220 2320 4220 4320 n/a n/a n/a plusw1 2220 2320 4220 4320 n/a n/a n/a legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2003 microchip technology inc. ds39599c-page 47 pic18f2220/2320/4220/4320 fsr1h 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu fsr1l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu bsr 2220 2320 4220 4320 ---- 0000 ---- 0000 ---- uuuu indf2 2220 2320 4220 4320 n/a n/a n/a postinc2 2220 2320 4220 4320 n/a n/a n/a postdec2 2220 2320 4220 4320 n/a n/a n/a preinc2 2220 2320 4220 4320 n/a n/a n/a plusw2 2220 2320 4220 4320 n/a n/a n/a fsr2h 2220 2320 4220 4320 ---- xxxx ---- uuuu ---- uuuu fsr2l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu status 2220 2320 4220 4320 ---x xxxx ---u uuuu ---u uuuu tmr0h 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu tmr0l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu t0con 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu osccon 2220 2320 4220 4320 0000 q000 0000 q000 uuuu qquu lvdcon 2220 2320 4220 4320 --00 0101 --00 0101 --uu uuuu wdtcon 2220 2320 4220 4320 ---- ---0 ---- ---0 ---- ---u rcon (4) 2220 2320 4220 4320 0--1 11q0 0--q qquu u--u qquu tmr1h 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu tmr1l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu t1con 2220 2320 4220 4320 0000 0000 u0uu uuuu uuuu uuuu tmr2 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu pr2 2220 2320 4220 4320 1111 1111 1111 1111 1111 1111 t2con 2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu sspbuf 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu sspadd 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu sspstat 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu sspcon1 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu sspcon2 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu table 4-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f2220/2320/4220/4320 ds39599c-page 48 ? 2003 microchip technology inc. adresh 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu adresl 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu adcon0 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu adcon1 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu adcon2 2220 2320 4220 4320 0-00 0000 0-00 0000 u-uu uuuu ccpr1h 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu ccpr2h 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu ccp2con 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu pwm1con 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu eccpas 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu cvrcon 2220 2320 4220 4320 000- 0000 000- 0000 uuu- uuuu cmcon 2220 2320 4220 4320 0000 0111 0000 0111 uuuu uuuu tmr3h 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu tmr3l 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu t3con 2220 2320 4220 4320 0000 0000 uuuu uuuu uuuu uuuu spbrg 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu rcreg 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu txreg 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu txsta 2220 2320 4220 4320 0000 -010 0000 -010 uuuu -uuu rcsta 2220 2320 4220 4320 0000 000x 0000 000x uuuu uuuu eeadr 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu eedata 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu eecon1 2220 2320 4220 4320 xx-0 x000 uu-0 u000 uu-0 u000 eecon2 2220 2320 4220 4320 0000 0000 0000 0000 0000 0000 table 4-3: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
? 2003 microchip technology inc. ds39599c-page 49 pic18f2220/2320/4220/4320 ipr2 2220 2320 4220 4320 11-1 1111 11-1 1111 uu-u uuuu pir2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu (1) pie2 2220 2320 4220 4320 00-0 0000 00-0 0000 uu-u uuuu ipr1 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu 2220 2320 4220 4320 -111 1111 -111 1111 -uuu uuuu pir1 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu (1) 2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu (1) pie1 2220 2320 4220 4320 0000 0000 0000 0000 uuuu uuuu 2220 2320 4220 4320 -000 0000 -000 0000 -uuu uuuu osctune 2220 2320 4220 4320 --00 0000 --00 0000 --uu uuuu trise 2220 2320 4220 4320 0000 -111 0000 -111 uuuu -uuu trisd 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu trisc 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu trisb 2220 2320 4220 4320 1111 1111 1111 1111 uuuu uuuu trisa (5) 2220 2320 4220 4320 1111 1111 (5) 1111 1111 (5) uuuu uuuu (5) late 2220 2320 4220 4320 ---- -xxx ---- -uuu ---- -uuu latd 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu latc 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu latb 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu lata (5) 2220 2320 4220 4320 xxxx xxxx (5) uuuu uuuu (5) uuuu uuuu (5) porte 2220 2320 4220 4320 ---- xxxx ---- xxxx ---- uuuu portd 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu portc 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu portb 2220 2320 4220 4320 xxxx xxxx uuuu uuuu uuuu uuuu porta (5) 2220 2320 4220 4320 xx0x 0000 (5) uu0u 0000 (5) uuuu uuuu (5) table 4-3: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets wdt reset reset instruction stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 4: see table 4-2 for reset value for specific condition. 5: bits 6 and 7 of porta, lata and trisa are enabled, depending on the oscillator mode selected. when not enabled as porta pins, they are disabled and read ? 0 ?.
pic18f2220/2320/4220/4320 ds39599c-page 50 ? 2003 microchip technology inc. figure 4-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 4-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 4-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ost
? 2003 microchip technology inc. ds39599c-page 51 pic18f2220/2320/4220/4320 figure 4-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) figure 4-7: time-out sequence on por w/ pll enabled (mclr tied to v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset 0v 1v 5v t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time-out ost time-out internal reset pll time-out t pll note: t ost = 1024 clock cycles. t pll 2 ms max. first three stages of the pwrt timer.
pic18f2220/2320/4220/4320 ds39599c-page 52 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 53 pic18f2220/2320/4220/4320 5.0 memory organization there are three memory types in enhanced mcu devices. these memory types are: program memory data ram data eeprom data and program memory use separate busses which allow for concurrent access of these types. additional detailed information for flash program mem- ory and data eeprom is provided in section 6.0 ?flash program memory? and section 7.0 ?data eeprom memory? , respectively. figure 5-1: program memory map and stack for pic18f2220/4220 5.1 program memory organization a 21-bit program counter is capable of addressing the 2-mbyte program memory space. accessing a location between the physically implemented memory and the 2-mbyte address will cause a read of all ? 0 ?s (a nop instruction). the pic18f2220 and pic18f4220 each have 4 kbytes of flash memory and can store up to 2,048 single-word instructions. the pic18f2320 and pic18f4320 each have 8 kbytes of flash memory and can store up to 4,096 single-word instructions. the reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. the program memory maps for pic18f2220/4220 and pic18f2320/4320 devices are shown in figure 5-1 and figure 5-2, respectively. figure 5-2: program memory map and stack for pic18f2320/4320 pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h on-chip program memory high priority interrupt vector 0008h user memory space 1fffffh 1000h 0fffh read ? 0 ? 200000h pc<20:0> stack level 1 ? stack level 31 reset vector low priority interrupt vector ? ? call,rcall,return retfie,retlw 21 0000h 0018h 2000h 1fffh on-chip program memory high priority interrupt vector 0008h user memory space read ? 0 ? 1fffffh 200000h
pic18f2220/2320/4220/4320 ds39599c-page 54 ? 2003 microchip technology inc. 5.2 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc (program counter) is pushed onto the stack when a call or rcall instruction is executed or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction. pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all resets. there is no ram associated with stack pointer 00000b. this is only a reset value. during a call type instruction, causing a push onto the stack, the stack pointer is first incremented and the ram location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). during a return type instruction, causing a pop from the stack, the contents of the ram location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writ- able through the top-of-stack special file registers. data can also be pushed to, or popped from, the stack using the top-of-stack sfrs. status bits indicate if the stack is full, has overflowed or underflowed. 5.2.1 top-of-stack access the top of the stack is readable and writable. three register locations, tosu, tosh and tosl, hold the contents of the stack location pointed to by the stkptr register (figure 5-3). this allows users to implement a software stack if necessary. after a call, rcall or interrupt, the software can read the pushed value by reading the tosu, tosh and tosl registers. these values can be placed on a user defined software stack. at return time, the software can replace the tosu, tosh and tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. 5.2.2 return stack pointer (stkptr) the stkptr register (register 5-1) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bits. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. at reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 23.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push, and stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or a por occurs. figure 5-3: return address stack and associated registers note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack top-of-stack 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0>
? 2003 microchip technology inc. ds39599c-page 55 pic18f2220/2320/4220/4320 register 5-1: stkptr register 5.2.3 push and pop instructions since the top-of-stack (tos) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable option. to push the current pc value onto the stack, a push instruction can be executed. this will increment the stack pointer and load the cur- rent pc value onto the stack. tosu, tosh and tosl can then be modified to place data or a return address on the stack. the ability to pull the tos value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the pop instruction. the pop instruc- tion discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. 5.2.4 stack full/underflow resets these resets are enabled by programming the stvren bit in configuration register 4l. when the stvren bit is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit but not cause a device reset. when the stvren bit is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. the stkful or stkunf bits are cleared by the user software or a por reset. r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful stkunf ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 bit 7 (1) stkful: stack full flag bit 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 (1) stkunf: stack underflow flag bit 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. legend: r = readable bit w = writable bit u = unimplemented c = clearable only bit - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 56 ? 2003 microchip technology inc. 5.3 fast register stack a ?fast return? option is available for interrupts. a fast register stack is provided for the status, wreg and bsr registers and are only one in depth. the stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. the values in the registers are then loaded back into the working registers if the retfie, fast instruction is used to return from the interrupt. all interrupt sources will push values into the stack reg- isters. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority inter- rupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label, fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return, fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.4 pcl, pclath and pclatu the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21-bits wide. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits and is not directly readable or writable. updates to the pch register may be per- formed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits and is not directly readable or writable. updates to the pcu register may be performed through the pclatu register. the contents of pclath and pclatu will be trans- ferred to the program counter by any operation that writes pcl. similarly, the upper two bytes of the pro- gram counter will be transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.8.1 ?computed goto ? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the lsb of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call, rcall, goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return fast ;restore values saved ;in fast register stack
? 2003 microchip technology inc. ds39599c-page 57 pic18f2220/2320/4220/4320 5.5 clocking scheme/instruction cycle the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pro- gram counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruc- tion is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-4. 5.6 instruction flow/pipelining an ?instruction cycle? consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 5-2). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?instruction register? (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 5-4: clock/ instruction cycle example 5-2: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc+2 pc+4 fetch inst (pc) execute inst (pc-2) fetch inst (pc+2) execute inst (pc) fetch inst (pc+4) execute inst (pc+2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1
pic18f2220/2320/4220/4320 ds39599c-page 58 ? 2003 microchip technology inc. 5.7 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). figure 5-5 shows an example of how instruction words are stored in the pro- gram memory. to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 5.4 ?pcl, pclath and pclatu? ). the call and goto instructions have the absolute pro- gram memory address embedded into the instruction. since instructions are always stored on word bound- aries, the data contained in the instruction is a word address. the word address is written to pc<20:1>, which accesses the desired byte address in program memory. instruction #2 in figure 5-5 shows how the instruction ? goto 000006h ? is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction repre- sents the number of single-word instructions that the pc will be offset by. section 24.0 ?instruction set summary? provides further details of the instruction set. figure 5-5: instructions in program memory 5.7.1 two-word instructions pic18f2x20/4x20 devices have four two-word instruc- tions: movff, call, goto and lfsr . the second word of these instructions has the 4 msbs set to ? 1 ?s and is decoded as a nop instruction. the lower 12 bits of the second word contain data to be used by the instruction. if the first word of the instruction is exe- cuted, the data in the second word is accessed. if the second word of the instruction is executed by itself (first word was skipped), it will execute as a nop . this action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip opera- tion. a program example that demonstrates this con- cept is shown in example 5-3. refer to section 24.0 ?instruction set summary? for further details of the instruction set. example 5-3: two-word instructions word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 000006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code
? 2003 microchip technology inc. ds39599c-page 59 pic18f2220/2320/4220/4320 5.8 look-up tables look-up tables are implemented two ways: computed goto table reads 5.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 5-4. a look-up table can be formed with an addwf pcl instruction and a group of retlw 0xnn instructions. wreg is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw 0xnn instructions that returns the value 0xnn to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-4: computed goto using an offset value 5.8.2 table reads/table writes a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per pro- gram word by using table reads and writes. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from, or written to program memory. data is transferred to/from program memory, one byte at a time. the table read/table write operation is discussed further in section 6.1 ?table reads and table writes? . 5.9 data memory organization the data memory is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. figure 5-6 shows the data memory organization for the pic18f2x20/4x20 devices. the data memory map is divided into as many as 16 banks that contain 256 bytes each. the lower 4 bits of the bank select register (bsr<3:0>) select which bank will be accessed. the upper 4 bits of the bsr are not implemented. the data memory contains special function registers (sfr) and general purpose registers (gpr). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratch pad operations in the user?s appli- cation. the sfrs start at the last location of bank 15 (fffh) and extend towards f80h. any remaining space beyond the sfrs in the bank may be implemented as gprs. gprs start at the first location of bank 0 and grow upwards. any read of an unimplemented location will read as ? 0 ?s. the entire data memory may be accessed directly or indirectly. direct addressing may require the use of the bsr register. indirect addressing requires the use of a file select register (fsrn) and a corresponding indi- rect file operand (indfn). each fsr holds a 12-bit address value that can be used to access any location in the data memory map without banking. see section 5.12 ?indirect addressing, indf and fsr registers? for indirect addressing details. the instruction set and architecture allow operations across all banks. this may be accomplished by indirect addressing or by the use of the movff instruction. the movff instruction is a two-word/two-cycle instruction that moves a value from one register to another. to ensure that commonly used registers (sfrs and select gprs) can be accessed in a single cycle, regardless of the current bsr values, an access bank is implemented. a segment of bank 0 and a segment of bank 15 comprise the access ram. section 5.10 ?access bank? provides a detailed description of the access ram. 5.9.1 general purpose register file enhanced mcu devices may have banked memory in the gpr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. data ram is available for use as gpr registers by all instructions. the second half of bank 15 (f80h to fffh) contains sfrs. all other banks of data memory contain gprs, starting with bank 0. movfw offset call table org 0xnn00 table addwf pcl retlw 0xnn retlw 0xnn retlw 0xnn
pic18f2220/2320/4220/4320 ds39599c-page 60 ? 2003 microchip technology inc. figure 5-6: data memory map for pic18f2x20/4x20 devices bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 080h 07fh f80h fffh 00h 7fh 80h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 128 bytes are general purpose ram (from bank 0). the second 128 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. f7fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr unused access ram high access ram low bank 2 to 200h unused read ? 00h ? = 1110 = 0010 (sfrs)
? 2003 microchip technology inc. ds39599c-page 61 pic18f2220/2320/4220/4320 5.9.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. a list of these registers is given in table 5-1 and table 5-2. the sfrs can be classified into two sets: those asso- ciated with the ?core? function and those related to the peripheral functions. those registers related to the ?core? are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. the sfrs are typically distributed among the peripherals whose functions they control. the unused sfr locations will be unimplemented and read as ? 0 ?s. table 5-1: special function register map for pic18f2x20/4x20 devices address name address name address name address name fffh tosu fdfh indf2 (2) fbfh ccpr1h f9fh ipr1 ffeh tosh fdeh postinc2 (2) fbeh ccpr1l f9eh pir1 ffdh tosl fddh postdec2 (2) fbdh ccp1con f9dh pie1 ffch stkptr fdch preinc2 (2) fbch ccpr2h f9ch ? ffbh pclatu fdbh plusw2 (2) fbbh ccpr2l f9bh osctune ffah pclath fdah fsr2h fbah ccp2con f9ah ? ff9h pcl fd9h fsr2l fb9h ? f99h ? ff8h tblptru fd8h status fb8h ? f98h ? ff7h tblptrh fd7h tmr0h fb7h pwm1con (1) f97h ? ff6h tblptrl fd6h tmr0l fb6h eccpas (1) f96h trise (1) ff5h tablat fd5h t0con fb5h cvrcon f95h trisd (1) ff4h prodh fd4h ? fb4h cmcon f94h trisc ff3h prodl fd3h osccon fb3h tmr3h f93h trisb ff2h intcon fd2h lvdcon fb2h tmr3l f92h trisa ff1h intcon2 fd1h wdtcon fb1h t3con f91h ? ff0h intcon3 fd0h rcon fb0h ? f90h ? fefh indf0 (2) fcfh tmr1h fafh spbrg f8fh ? feeh postinc0 (2) fceh tmr1l faeh rcreg f8eh ? fedh postdec0 (2) fcdh t1con fadh txreg f8dh late (1) fech preinc0 (2) fcch tmr2 fach txsta f8ch latd (1) febh plusw0 (2) fcbh pr2 fabh rcsta f8bh latc feah fsr0h fcah t2con faah ? f8ah latb fe9h fsr0l fc9h sspbuf fa9h eeadr f89h lata fe8h wreg fc8h sspadd fa8h eedata f88h ? fe7h indf1 (2) fc7h sspstat fa7h eecon2 f87h ? fe6h postinc1 (2) fc6h sspcon1 fa6h eecon1 f86h ? fe5h postdec1 (2) fc5h sspcon2 fa5h ? f85h ? fe4h preinc1 (2) fc4h adresh fa4h ? f84h porte fe3h plusw1 (2) fc3h adresl fa3h ? f83h portd (1) fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb fe0h bsr fc0h adcon2 fa0h pie2 f80h porta legend: ? = unimplemented registers, read as ? 0 ?. note 1: this register is not available on pic18f2x20 devices. 2: this is not a physical register.
pic18f2220/2320/4220/4320 ds39599c-page 62 ? 2003 microchip technology inc. table 5-2: register file summary (pic18f2220/2320/4220/4320) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: tosu ? ? ? top-of-stack upper byte (tos<20:16>) ---0 0000 46, 54 tosh top-of-stack high byte (tos<15:8>) 0000 0000 46, 54 tosl top-of-stack low byte (tos<7:0>) 0000 0000 46, 54 stkptr stkful stkunf ? return stack pointer 00-0 0000 46, 55 pclatu ? ?bit 21 (3) holding register for pc<20:16> ---0 0000 46, 56 pclath holding register for pc<15:8> 0000 0000 46, 56 pcl pc low byte (pc<7:0>) 0000 0000 46, 56 tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 46, 74 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 46, 74 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 46, 74 tablat program memory table latch 0000 0000 46, 74 prodh product register high byte xxxx xxxx 46, 85 prodl product register low byte xxxx xxxx 46, 85 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 46, 89 intcon2 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?rbip 1111 -1-1 46, 90 intcon3 int2ip int1ip ?int2ieint1ie ? int2if int1if 11-0 0-00 46, 91 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 46, 66 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 46, 66 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 46, 66 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 46, 66 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 offset by w (not a physical register) n/a 46, 66 fsr0h ? ? ? ? indirect data memory address pointer 0 high ---- 0000 46, 66 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 46, 66 wreg working register xxxx xxxx 46 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 46, 66 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 46, 66 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 46, 66 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 46, 66 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 offset by w (not a physical register) n/a 46, 66 fsr1h ? ? ? ? indirect data memory address pointer 1 high ---- 0000 47, 66 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 47, 66 bsr ? ? ? ? bank select register ---- 0000 47, 65 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 47, 66 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 47, 66 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 47, 66 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 47, 66 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 offset by w (not a physical register) n/a 47, 66 fsr2h ? ? ? ? indirect data memory address pointer 2 high ---- 0000 47, 66 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 47, 66 status ? ? ?novzdcc ---x xxxx 47, 68 tmr0h timer0 register high byte 0000 0000 47, 119 tmr0l timer0 register low byte xxxx xxxx 47, 119 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 47, 117 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio, ecio and intio2 (with port function on ra6) oscillator mode only a nd read ? 0 ? in all other oscillator modes. 2: ra7 and associated bits are configured as port pins in intio2 oscillator mode only and read ? 0 ? in all other modes. 3: bit 21 of the pc is only available in test mode and serial programming modes. 4: if pbaden = 0 , portb<4:0> are configured as digital input and read unknown and if pbaden = 1 , portb<4:0> are configured as analog input and read ? 0 ? following a reset. 5: these registers and/or bits are not implemented on the pic18f2x20 devices and read as ? 0 ?. 6: the re3 port bit is only available when mclre fuse (config3h<7>) is programmed to ? 0 ?. otherwise, re3 reads ? 0 ?. this bit is read-only.
? 2003 microchip technology inc. ds39599c-page 63 pic18f2220/2320/4220/4320 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 q000 26, 47 lvdcon ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 --00 0101 47, 233 wdtcon ? ? ? ? ? ? ?swdten --- ---0 47, 246 rcon ipen ? ?ri to pd por bor 0--1 11q0 45, 69, 98 tmr1h timer1 register high byte xxxx xxxx 47, 125 tmr1l timer1 register low byte xxxx xxxx 47, 125 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 47, 121 tmr2 timer2 register 0000 0000 47, 127 pr2 timer2 period register 1111 1111 47, 127 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 47, 127 sspbuf ssp receive buffer/transmit register xxxx xxxx 47, 156, 164 sspadd ssp address register in i 2 c slave mode. ssp baud rate reload register in i 2 c master mode. 0000 0000 47, 164 sspstat smp cke d/a psr/w ua bf 0000 0000 47, 156, 165 sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 47, 157, 166 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 47, 167 adresh a/d result register high byte xxxx xxxx 48, 220 adresl a/d result register low byte xxxx xxxx 48, 220 adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon --00 0000 48, 211 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 48, 212 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 48, 213 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 48, 134 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 48, 134 ccp1con p1m1 (5) p1m0 (5) dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 48, 133, 141 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx 48, 134 ccpr2l capture/compare/pwm register 2 low byte xxxx xxxx 48, 134 ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 48, 133 pwm1con (5) prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 48, 149 eccpas (5) eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 48, 150 cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 48, 227 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 48, 221 tmr3h timer3 register high byte xxxx xxxx 48, 131 tmr3l timer3 register low byte xxxx xxxx 48, 131 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 48, 129 spbrg usart baud rate generator 0000 0000 48, 198 rcreg usart receive register 0000 0000 48, 204, 203 txreg usart transmit register 0000 0000 48, 202, 203 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 48, 196 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 48, 197 table 5-2: register file summary (pic18f2220/2320/4220/4320) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio, ecio and intio2 (with port function on ra6) oscillator mode only a nd read ? 0 ? in all other oscillator modes. 2: ra7 and associated bits are configured as port pins in intio2 oscillator mode only and read ? 0 ? in all other modes. 3: bit 21 of the pc is only available in test mode and serial programming modes. 4: if pbaden = 0 , portb<4:0> are configured as digital input and read unknown and if pbaden = 1 , portb<4:0> are configured as analog input and read ? 0 ? following a reset. 5: these registers and/or bits are not implemented on the pic18f2x20 devices and read as ? 0 ?. 6: the re3 port bit is only available when mclre fuse (config3h<7>) is programmed to ? 0 ?. otherwise, re3 reads ? 0 ?. this bit is read-only.
pic18f2220/2320/4220/4320 ds39599c-page 64 ? 2003 microchip technology inc. eeadr eeprom address register 0000 0000 48, 81 eedata eeprom data register 0000 0000 48, 84 eecon2 eeprom control register 2 (not a physical register) 0000 0000 48, 72, 81 eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 48, 73, 82 ipr2 oscfip cmip ? eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 49, 97 pir2 oscfif cmif ? eeif bclif lvdif tmr3if ccp2if 00-0 0000 49, 93 pie2 oscfie cmie ? eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 49, 95 ipr1 pspip (5) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 49, 96 pir1 pspif (5) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 49, 92 pie1 pspie (5) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 49, 94 osctune ? ? tun5 tun4 tun3 tun2 tun1 tun0 --00 0000 23, 49 trise (5) ibf obf ibov pspmode ? data direction bits for porte (5) 0000 -111 49, 112 trisd (5) data direction control register for portd 1111 1111 49, 110 trisc data direction control register for portc 1111 1111 49, 108 trisb data direction control register for portb 1111 1111 49, 106 trisa trisa7 (2) trisa6 (1) data direction control register for porta 1111 1111 49, 103 late (5) ? ? ? ? ? read/write porte data latch ---- -xxx 49, 113 latd (5) read/write portd data latch xxxx xxxx 49, 110 latc read/write portc data latch xxxx xxxx 49, 108 latb read/write portb data latch xxxx xxxx 49, 106 lata lata<7> (2) lata<6> (1) read/write porta data latch xxxx xxxx 49, 103 porte ? ? ? ?re3 (6) read porte pins, write porte data latch (5) ---- xxxx 49, 113 portd read portd pins, write portd data latch xxxx xxxx 49, 110 portc read portc pins, write portc data latch xxxx xxxx 49, 108 portb read portb pins, write portb data latch (4) xxxx xxxx 49, 106 porta ra7 (2) ra6 (1) read porta pins, write porta data latch xx0x 0000 49, 103 table 5-2: register file summary (pic18f2220/2320/4220/4320) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition note 1: ra6 and associated bits are configured as port pins in rcio, ecio and intio2 (with port function on ra6) oscillator mode only a nd read ? 0 ? in all other oscillator modes. 2: ra7 and associated bits are configured as port pins in intio2 oscillator mode only and read ? 0 ? in all other modes. 3: bit 21 of the pc is only available in test mode and serial programming modes. 4: if pbaden = 0 , portb<4:0> are configured as digital input and read unknown and if pbaden = 1 , portb<4:0> are configured as analog input and read ? 0 ? following a reset. 5: these registers and/or bits are not implemented on the pic18f2x20 devices and read as ? 0 ?. 6: the re3 port bit is only available when mclre fuse (config3h<7>) is programmed to ? 0 ?. otherwise, re3 reads ? 0 ?. this bit is read-only.
? 2003 microchip technology inc. ds39599c-page 65 pic18f2220/2320/4220/4320 5.10 access bank the access bank is an architectural enhancement which is very useful for c compiler code optimization. the techniques used by the c compiler may also be useful for programs written in assembly. this data memory region can be used for: intermediate computational values local variables of subroutines faster context saving/switching of variables common variables faster evaluation/control of sfrs (no banking) the access bank is comprised of the last 128 bytes in bank 15 (sfrs) and the first 128 bytes in bank 0. these two sections will be referred to as access ram high and access ram low, respectively. figure 5-6 indicates the access ram areas. a bit in the instruction word specifies if the operation is to occur in the bank specified by the bsr register or in the access bank. this bit is denoted as the ?a? bit (for access bit). when forced in the access bank (a = 0 ), the last address in access ram low is followed by the first address in access ram high. access ram high maps the special function registers, so these registers can be accessed without any software overhead. this is useful for testing status flags and modifying control bits. 5.11 bank select register (bsr) the need for a large general purpose memory space dictates a ram banking scheme. the data memory is partitioned into as many as sixteen banks. when using direct addressing, the bsr should be configured for the desired bank. bsr<3:0> holds the upper 4 bits of the 12-bit ram address. the bsr<7:4> bits will always read ? 0 ?s and writes will have no effect (see figure 5-7). a movlb instruction has been provided in the instruction set to assist in selecting banks. if the currently selected bank is not implemented, any read will return all ? 0 ?s and all writes are ignored. the status register bits will be set/cleared as appropriate for the instruction performed. each bank extends up to ffh (256 bytes). all data memory is implemented as static ram. a movff instruction ignores the bsr since the 12-bit addresses are embedded into the instruction word. section 5.12 ?indirect addressing, indf and fsr registers? provides a description of indirect address- ing which allows linear addressing of the entire ram space. figure 5-7: direct addressing note 1: for register file map detail, see table 5-1. 2: the access bit of the instruction can be used to forc e an override of the selected bank (bsr<3:0>) to the registers of the access bank. 3: the movff instruction embeds the entire 12-bit address in the instruction. data memory (1) direct addressing bank select (2) location select (3) bsr<3:0> 7 0 from opcode (3) 00h 01h 0eh 0fh bank 0 bank 1 bank 14 bank 15 1ffh 100h 0ffh 000h effh e00h fffh f00h bsr<7:4> 0000
pic18f2220/2320/4220/4320 ds39599c-page 66 ? 2003 microchip technology inc. 5.12 indirect addressing, indf and fsr registers indirect addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. an fsr register is used as a pointer to the data memory location that is to be read or written. since this pointer is in ram, the contents can be modified by the program. this can be useful for data tables in the data memory and for software stacks. figure 5-8 shows how the fetched instruction is modified prior to being executed. indirect addressing is possible by using one of the indf registers. any instruction using the indf register actually accesses the register pointed to by the file select register, fsr. reading the indf register itself, indirectly (fsr = 0 ), will read 00h. writing to the indf register indirectly, results in a no operation. the fsr register contains a 12-bit address which is shown in figure 5-9. the indfn register is not a physical register. address- ing indfn actually addresses the register whose address is contained in the fsrn register (fsrn is a pointer); this is indirect addressing. example 5-5 shows a simple use of indirect addressing to clear the ram in bank 1 (locations 100h-1ffh) in a minimum number of instructions. example 5-5: how to clear ram (bank 1) using indirect addressing there are three indirect addressing registers. to address the entire data memory space (4096 bytes), these registers are 12 bits wide. to store the 12 bits of addressing information, two 8-bit registers are required: 1. fsr0: composed of fsr0h:fsr0l 2. fsr1: composed of fsr1h:fsr1l 3. fsr2: composed of fsr2h:fsr2l in addition, there are registers indf0, indf1 and indf2, which are not physically implemented. reading or writing to these registers activates indirect address- ing with the value in the corresponding fsr register being the address of the data. if an instruction writes a value to indf0, the value will be written to the address pointed to by fsr0h:fsr0l. a read from indf1 reads the data from the address pointed to by fsr1h:fsr1l. indfn can be used in code anywhere an operand can be used. if indf0, indf1 or indf2 are read indirectly via an fsr, all ? 0 ?s are read (zero bit is set). similarly, if indf0, indf1 or indf2 are written to indirectly, the operation will be equivalent to a nop instruction and the status bits are not affected. 5.12.1 indirect addressing operation each fsr register has an indf register associated with it, plus four additional register addresses. perform- ing an operation using one of these five registers determines how the fsr will be modified during indirect addressing. when data access is performed using one of the five indfn locations, the address selected will configure the fsrn register to: do nothing to fsrn after an indirect access (no change) ? indfn auto-decrement fsrn after an indirect access (post-decrement) ? postdecn auto-increment fsrn after an indirect access (post-increment) ? postincn auto-increment fsrn before an indirect access (pre-increment) ? preincn use the value in the wreg register as an offset to fsrn. do not modify the value of the wreg or the fsrn register after an indirect access (no change) ? pluswn when using the auto-increment or auto-decrement features, the effect on the fsr is not reflected in the status register. for example, if the indirect address causes the fsr to equal ? 0 ?, the z bit will not be set. auto-incrementing or auto-decrementing an fsr affects all 12 bits. that is, when fsrnl overflows from an increment, fsrnh will be incremented automatically. adding these features allows the fsrn to be used as a stack pointer, in addition to its use for table operations in data memory. each fsr has an address associated with it that per- forms an indexed indirect access. when a data access to this indfn location (pluswn) occurs, the fsrn is configured to add the signed value in the wreg regis- ter and the value in fsr to form the address before an indirect access. the fsr value is not changed. the wreg offset range is -128 to +127. if an fsr register contains a value that points to one of the indfn, an indirect read will read 00h (zero bit is set) while an indirect write will be equivalent to a nop (status bits are not affected). if an indirect addressing write is performed when the target address is an fsrnh or fsrnl register, the data is written to the fsr register but no pre- or post-increment/decrement is performed. lfsr fsr0,0x100 ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? goto next ; no, clear next continue ; yes, continue
? 2003 microchip technology inc. ds39599c-page 67 pic18f2220/2320/4220/4320 figure 5-8: indirect addressing operation figure 5-9: indirect addressing opcode address file address = access of an indirect addressing register fsr instruction executed instruction fetched ram opcode file 12 12 12 bsr<3:0> 8 4 0h fffh note 1: for register file map detail, see table 5-1. data memory (1) indirect addressing fsrnh:fsrnl 30 0fffh 0000h location select 11 0 07
pic18f2220/2320/4220/4320 ds39599c-page 68 ? 2003 microchip technology inc. 5.13 status register the status register, shown in register 5-2, contains the arithmetic status of the alu. the status register can be the operand for any instruction as with any other regis- ter. if the status register is the destination for an instruc- tion that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, movff and movwf instructions are used to alter the status register, because these instructions do not affect the z, c, dc, ov or n bits in the status reg- ister. for other instructions not affecting any status bits, see table 24-2. register 5-2: status register note: the c and dc bits operate as a borrow and digit borrow bit respectively, in subtraction. u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?novzdcc bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit for addwf, addlw, sublw and subwf instructions. 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result note: for borrow, the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 0 c: carry/borrow bit for addwf, addlw, sublw and subwf instructions. 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note: for borrow, the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf, rlf ) instructions, this bit is loaded with either the high or low order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 69 pic18f2220/2320/4220/4320 5.14 rcon register the reset control (rcon) register contains flag bits that allow differentiation between the sources of a device reset. these flags include the to , pd , por , bor and ri bits. this register is readable and writable. register 5-3: rcon register note 1: if the boren configuration bit is set (brown-out reset enabled), the bor bit is ? 1 ? on a power-on reset. after a brown- out reset has occurred, the bor bit will be cleared and must be set by firmware to indicate the occurrence of the next brown-out reset. 2: it is recommended that the por bit be set after a power-on reset has been detected so that subsequent power-on resets may be detected. r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = cleared by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 70 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 71 pic18f2220/2320/4220/4320 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 8 bytes at a time. program memory is erased in blocks of 64 bytes at a time. a bulk erase operation may not be issued from user code. while writing or erasing program memory, instruction fetches cease until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: table read ( tblrd ) table write ( tblwt ) the program memory space is 16 bits wide while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into tablat in the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from tablat in the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word aligned (tblptrl<0> = 0 ). the eeprom on-chip timer controls the write and erase times. the write and erase voltages are gener- ated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. figure 6-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer points to a byte in program memory. program memory (tblptr)
pic18f2220/2320/4220/4320 ds39599c-page 72 ? 2003 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: eecon1 register eecon2 register tablat register tblptr registers 6.2.1 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit, eepgd, determines if the access will be to program or data eeprom memory. when clear, operations will access the data eeprom memory. when set, program memory is accessed. control bit, cfgs, determines if the access will be to the configuration registers or to program memory/data eeprom memory. when set, subsequent operations access configuration registers. when cfgs is clear, the eepgd bit selects either program flash or data eeprom memory. the free bit controls program memory erase opera- tions. when the free bit is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit enables and disables erase and write operations. when set, erase and write operations are allowed. when clear, erase and write operations are disabled ? the wr bit cannot be set while the wren bit is clear. this process helps to prevent accidental writes to memory due to errant (unexpected) code execution. firmware should keep the wren bit clear at all times except when starting erase or write operations. once firmware has set the wr bit, the wren bit may be cleared. clearing the wren bit will not affect the operation in progress. the wrerr bit is set when a write operation is inter- rupted by a reset. in these situations, the user can check the wrerr bit and rewrite the location. it will be necessary to reload the data and address registers (eedata and eeadr) as these registers have cleared as a result of the reset. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 6.3 ?reading the flash program memory? regarding table reads. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of eight holdi ng registers, the address of which is determined by tblptrl<2:0>. the process for physically writing dat a to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: interrupt flag bit, eeif in the pir2 register, is set when the write is complete. it must be cleared in software.
? 2003 microchip technology inc. ds39599c-page 73 pic18f2220/2320/4220/4320 register 6-1: eecon1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data ee or configuration select bit 1 = access configuration registers 0 = access program flash or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation ? tblptr<5:0> are ignored) 0 = perform write only bit 3 wrerr: eeprom error flag bit 1 = a write operation was prematurely terminated (any reset during self-timed programming) 0 = the write operation completed normally note: when a wrerr occurs, the eepgd and cfgs bits are not cleared. this allows tracing of the error condition. bit 2 wren: write enable bit 1 = allows erase or write cycles 0 = inhibits erase or write cycles bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle completed bit 0 rd: read control bit 1 = initiates a memory read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = read completed legend: r = readable bit s = settable only u = unimplemented bit, read as ?0? w = writable bit - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 74 ? 2003 microchip technology inc. 6.2.2 tablat ? table latch register the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 tblptr ? table pointer register the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low order 21 bits allow the device to address up to 2 mbytes of program memory space. setting the 22nd bit allows access to the device id, the user id and the configuration bits. the table pointer, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table opera- tion. these operations are shown in table 6-1. these operations on the tblptr only affect the low order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the table pointer determine which byte is read from program or configuration memory into tablat. when a tblwt is executed, the three lsbs of the table pointer (tblptr<2:0>) determine which of the eight program memory holding registers is written to. when the timed write to program memory (long write) begins, the 19 msbs of the tblptr (tblptr<21:3>) will deter- mine which program memory block of 8 bytes is written to (tblptr<2:0> are ignored). for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 16 msbs of the table pointer (tblptr<21:6>) point to the 64-byte block that will be erased. the least significant bits (tblptr<5:0>) are ignored. figure 6-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 6-1: table pointer operations with tblrd and tblwt instructions figure 6-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 erase ? tblptr<21:6> long write ? tblptr<21:3> read or write ? tblptr<21:0> tblptrl tblptrh tblptru
? 2003 microchip technology inc. ds39599c-page 75 pic18f2220/2320/4220/4320 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and place it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing a tblrd instruction places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word odd (high) byte program memory even (low) byte tablat tblptr instruction register (ir) read register lsb = 1 tblptr lsb = 0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment tblptr movfw tablat ; get data movwf word_even tblrd*+ ; read into tablat and increment tblptr movfw tablat ; get data movwf word_odd
pic18f2220/2320/4220/4320 ds39599c-page 76 ? 2003 microchip technology inc. 6.4 erasing flash program memory the minimum erase block size is 32 words or 64 bytes under firmware control. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in flash memory is not supported. when initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased. the most significant 16 bits of the tblptr<21:6> point to the block being erased; tblptr<5:0> are ignored. the eecon1 register commands the erase operation. the eepgd bit must be set to point to the flash pro- gram memory. the cfgs bit must be clear to access program flash and data eeprom memory. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. the wr bit is set as part of the required instruction sequence (as shown in example 6-2) and starts the actual erase operation. it is not necessary to load the tablat register with any data as it is ignored. for protection, the write initiate sequence using eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer with address of row being erased. 2. set the eecon1 register for the erase operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable writes; set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. execute a nop . 9. re-enable interrupts. example 6-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1,eepgd ; point to flash program memory bsf eecon1,wren ; enable write to memory bsf eecon1,free ; enable row erase operation bcf intcon,gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h required movlw aah sequence movwf eecon2 ; write aah bsf eecon2,wr ; start erase (cpu stall) nop bsf intcon,gie ; re-enable interrupts
? 2003 microchip technology inc. ds39599c-page 77 pic18f2220/2320/4220/4320 6.5 writing to flash program memory the programming block size is 4 words or 8 bytes. word or byte programming is not supported. table writes are used internally to load the holding reg- isters needed to program the flash memory. there are 8 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction has to be executed 8 times for each programming operation. all of the table write operations will essentially be short writes because only the holding registers are written. at the end of updating 8 registers, the eecon1 register must be written to, to start the programming operation with a long write. the long write is necessary for programming the inter- nal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. figure 6-5: table writes to flash program memory 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. read 64 bytes into ram. 2. update data values in ram as necessary. 3. load table pointer with address being erased. 4. do the row erase procedure (see section 6.4.1 ?flash program memory erase sequence? ). 5. load table pointer with address of first byte being written. 6. write the first 8 bytes into the holding registers with auto-increment. 7. set the eecon1 register for the write operation: set eepgd bit to point to program memory; clear the cfgs bit to access program memory; set wren bit to enable byte writes. 8. disable interrupts. 9. write 55h to eecon2. 10. write aah to eecon2. 11. set the wr bit. this will begin the write cycle. 12. the cpu will stall for duration of the write (about 2 ms using internal timer). 13. execute a nop . 14. re-enable interrupts. 15. repeat steps 6-14 seven times, to write 64 bytes. 16. verify the memory (table read). this procedure will require about 18 ms to update one row of 64 bytes of memory. an example of the required code is given in example 6-3. holding register tablat holding register tblptr = xxxxx7 holding register tblptr = xxxxx1 holding register tblptr = xxxxx0 8 8 8 8 write register tblptr = xxxxx2 program memory
pic18f2220/2320/4220/4320 ds39599c-page 78 ? 2003 microchip technology inc. example 6-3: writing to flash program memory movlw d'64 ; number of bytes in erase block movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low ; 6 lsb = 0 movwf tblptrl read_block tblrd*+ ; read into tablat, and inc movfw tablat ; get data movwf postinc0 ; store data and increment fsr0 decfsz counter ; done? goto read_block ; repeat modify_word movlw data_addr_high ; point to buffer movwf fsr0h movlw data_addr_low movwf fsr0l movlw new_data_low ; update buffer word and increment fsr0 movwf postinc0 movlw new_data_high ; update buffer word movwf indf0 erase_block movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low ; 6 lsb = 0 movwf tblptrl bcf eecon1,cfgs ; point to prog/eeprom memory bsf eecon1,eepgd ; point to flash program memory bsf eecon1,wren ; enable write to memory bsf eecon1,free ; enable row erase operation bcf intcon,gie ; disable interrupts movlw 55h ; required sequence movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1,wr ; start erase (cpu stall) nop bsf intcon,gie ; re-enable interrupts write_buffer_back movlw 8 ; number of write buffer groups of 8 bytes movwf counter_hi movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l program_loop movlw 8 ; number of bytes in holding register movwf counter write_word_to_hregs movfw postinc0 ; get low byte of buffer data and increment fsr0 movwf tablat ; present data to table latch tblwt+* ; short write ; to internal tblwt holding register, increment tblptr decfsz counter ; loop until buffers are full goto write_word_to_hregs
? 2003 microchip technology inc. ds39599c-page 79 pic18f2220/2320/4220/4320 example 6-3: writing to flash program memory (continued) 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset, during normal operation. in these situations, users can check the wrerr bit and rewrite the location. 6.6 flash program operation during code protection see section 23.0 ?special features of the cpu? ( section 23.5 ?program verification and code pro- tection? ) for details on code protection of flash program memory. table 6-2: registers associated with program flash memory program_memory bcf intcon,gie ; disable interrupts movlw 55h ; required sequence movwf eecon2 ; write 55h movlw aah movwf eecon2 ; write aah bsf eecon1,wr ; start program (cpu stall) nop bsf intcon,gie ; re-enable interrupts decfsz counter_hi ; loop until done goto program_loop bcf eecon1,wren ; disable write to memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 --00 0000 tbpltrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 0000 0000 tblptrl program memory table pointer high byte (tblptr<7:0>) 0000 0000 0000 0000 tablat program memory table latch 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u eecon2 eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 oscfip cmip ? eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 ---1 1111 pir2 oscfif cmif ? eeif bclif lvdif tmr3if ccp2if 00-0 0000 ---0 0000 pie2 oscfie cmie ? eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 ---0 0000 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access.
pic18f2220/2320/4220/4320 ds39599c-page 80 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 81 pic18f2220/2320/4220/4320 7.0 data eeprom memory the data eeprom is readable and writable during nor- mal operation over the entire v dd range. the data memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (sfr). there are four sfrs used to read and write the program and data eeprom memory. these registers are: eecon1 eecon2 eedata eeadr the eeprom data memory allows byte read and write. when interfacing to the data memory block, eedata holds the 8-bit data for read/write and eeadr holds the address of the eeprom location being accessed. these devices have 256 bytes of data eeprom with an address range from 00h to ffh. the eeprom data memory is rated for high erase/write cycle endurance. a byte write automatically erases the location and writes the new data (erase-before-write). the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip to chip. please refer to parameter d122 (table 26-1 in section 26.0 ?electrical characteristics? ) for exact limits. 7.1 eeadr the address register can address 256 bytes of data eeprom. 7.2 eecon1 and eecon2 registers eecon1 is the control register for memory accesses. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the memory write and erase sequences. control bit eepgd determines if the access will be to program or data eeprom memory. when clear, oper- ations will access the data eeprom memory. when set, program memory is accessed. control bit cfgs determines if the access will be to the configuration registers or to program memory/data eeprom memory. when set, subsequent operations access configuration registers. when cfgs is clear, the eepgd bit selects either program flash or data eeprom memory. the wren bit enables and disables erase and write operations. when set, erase and write operations are allowed. when clear, erase and write operations are disabled; the wr bit cannot be set while the wren bit is clear. this mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. firmware should keep the wren bit clear at all times except when starting erase or write operations. once firmware has set the wr bit, the wren bit may be cleared. clearing the wren bit will not affect the operation in progress. the wrerr bit is set when a write operation is inter- rupted by a reset. in these situations, the user can check the wrerr bit and rewrite the location. it is nec- essary to reload the data and address registers (eedata and eeadr), as these registers have cleared as a result of the reset. control bits, rd and wr, start read and erase/write operations, respectively. these bits are set by firmware and cleared by hardware at the completion of the operation. the rd bit cannot be set when accessing program memory (eepgd = 1 ). program memory is read using table read instructions. see section 6.1 ?table reads and table writes? regarding table reads. note: interrupt flag bit, eeif in the pir2 register, is set when write is complete. it must be cleared in software.
pic18f2220/2320/4220/4320 ds39599c-page 82 ? 2003 microchip technology inc. register 7-1: eecon1 register r/w-x r/w-x u-0 r/w-0 r/w-x r/w-0 r/s-0 r/s-0 eepgd cfgs ? free wrerr wren wr rd bit 7 bit 0 bit 7 eepgd: flash program or data eeprom memory select bit 1 = access program flash memory 0 = access data eeprom memory bit 6 cfgs: flash program/data ee or configuration select bit 1 = access configuration or calibration registers 0 = access program flash or data eeprom memory bit 5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write only bit 3 wrerr: eeprom error flag bit 1 = a write operation was prematurely terminated (mclr or wdt reset during self-timed erase or program operation) 0 = the write operation completed normally note: when a wrerr occurs, the eepgd or free bits are not cleared. this allows tracing of the error condition. bit 2 wren: erase/write enable bit 1 = allows erase/write cycles 0 = inhibits erase/write cycles bit 1 wr: write control bit 1 = initiates a data eeprom erase/write cycle or a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle is completed bit 0 rd: read control bit 1 = initiates a memory read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. rd bit cannot be set when eepgd = 1 .) 0 = read completed legend: r = readable bit s = settable only u = unimplemented bit, read as ?0? w = writable bit - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 83 pic18f2220/2320/4220/4320 7.3 reading the data eeprom memory to read a data memory location, the user must write the address to the eeadr register, clear the eepgd con- trol bit (eecon1<7>) and then set control bit, rd (eecon1<0>). the data is available for the very next instruction cycle; therefore, the eedata register can be read by the next instruction. eedata will hold this value until another read operation or until it is written to by the user (during a write operation). 7.4 writing to the data eeprom memory to write an eeprom data location, the address must first be written to the eeadr register and the data written to the eedata register. the sequence in example 7-2 must be followed to initiate the write cycle. the write will not begin if this sequence is not exactly followed (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. it is strongly recom- mended that interrupts be disabled during this code segment. additionally, the wren bit in eecon1 must be set to enable writes. this mechanism prevents accidental writes to data eeprom due to unexpected code exe- cution (i.e., runaway programs). the wren bit should be kept clear at all times except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, eecon1, eeadr and eedata cannot be modified. the wr bit will be inhibited from being set unless the wren bit is set. the wren bit must be set on a previous instruc- tion. both wr and wren cannot be set with the same instruction. at the completion of the write cycle, the wr bit is cleared in hardware and the eeprom interrupt flag bit (eeif) is set. the user may either enable this interrupt or poll this bit. eeif must be cleared by software. 7.5 write verify depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 7.6 protection against spurious write there are conditions when the device may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built-in. on power-up, the wren bit is cleared. also, the power-up timer (72 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. example 7-1: data eeprom read example 7-2: data eeprom write movlw data_ee_addr ; movwf eeadr ; data memory address to read bcf eecon1, eepgd ; point to data memory bsf eecon1, rd ; eeprom read movf eedata, w ; w = eedata movlw data_ee_addr ; movwf eeadr ; data memory address to write movlw data_ee_data ; movwf eedata ; data memory value to write bcf eecon1, eepgd ; point to data memory bsf eecon1, wren ; enable writes bcf intcon, gie ; disable interrupts movlw 55h ; required movwf eecon2 ; write 55h sequence movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write bsf intcon, gie ; enable interrupts sleep ; wait for interrupt to signal write complete bcf eecon1, wren ; disable writes
pic18f2220/2320/4220/4320 ds39599c-page 84 ? 2003 microchip technology inc. 7.7 operation during code-protect data eeprom memory has its own code-protect bits in configuration words. external read and write opera- tions are disabled if either of these mechanisms are enabled. the microcontroller itself can both read and write to the internal data eeprom regardless of the state of the code-protect configuration bit. refer to section 23.0 ?special features of the cpu? for additional information. 7.8 using the data eeprom the data eeprom is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program vari- ables or other data that are updated often). frequently changing values will typically be updated more often than specification d124 or d124a. if this is not the case, an array refresh must be performed. for this reason, variables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. a simple data eeprom refresh routine is shown in example 7-3. example 7-3: data eeprom refresh routine table 7-1: registers associated with data eeprom memory note: if data eeprom is only used to store constants and/or data that changes rarely, an array refresh is likely not required. see specification d124 or d124a. clrf eeadr ; start at address 0 bcf eecon1, cfgs ; set for memory bcf eecon1, eepgd ; set for data eeprom bcf intcon, gie ; disable interrupts bsf eecon1, wren ; enable writes loop ; loop to refresh array bsf eecon1, rd ; read current address movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1, wr ; set wr bit to begin write btfsc eecon1, wr ; wait for write to complete bra $-2 incfsz eeadr, f ; increment address bra loop ; not zero, do it again bcf eecon1, wren ; disable writes bsf intcon, gie ; enable interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie inte rbie tmr0if intf rbif 0000 000x 0000 000u eeadr eeprom address register 0000 0000 0000 0000 eedata eeprom data register 0000 0000 0000 0000 eecon2 eeprom control register 2 (not a physical register) ? ? eecon1 eepgd cfgs ? free wrerr wren wr rd xx-0 x000 uu-0 u000 ipr2 oscfip cmip ?eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 ---1 1111 pir2 oscfif cmif ?eeif bclif lvdif tmr3if ccp2if 00-0 0000 ---0 0000 pie2 oscfie cmie ?eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 ---0 0000 legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access.
? 2003 microchip technology inc. ds39599c-page 85 pic18f2220/2320/4220/4320 8.0 8 x 8 hardware multiplier 8.1 introduction an 8 x 8 hardware multiplier is included in the alu of the pic18f2x20/4x20 devices. by making the multiply a hardware operation, it completes in a single instruc- tion cycle. this is an unsigned multiply that gives a 16-bit result. the result is stored into the 16-bit product register pair (prodh:prodl). the multiplier does not affect any flags in the status register. making the 8 x 8 multiplier execute in a single-cycle gives the following advantages: higher computational throughput reduces code size requirements for multiply algorithms the performance increase allows the device to be used in applications previously reserved for digital signal processors. table 8-1 shows a performance comparison between enhanced devices using the single-cycle hardware multiply and performing the same function without the hardware multiply. table 8-1: performance comparison 8.2 operation example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. only one instruction is required when one argument of the multiply is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiply. to account for the sign bits of the arguments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s 27.6 s 69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s 36.4 s 91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s 96.8 s 242 s hardware multiply 28 28 2.8 s11.2 s28 s 16 x 16 signed without hardware multiply 52 254 25.4 s102.6 s 254 s hardware multiply 35 40 4.0 s 16.0 s 40 s movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2
pic18f2220/2320/4220/4320 ds39599c-page 86 ? 2003 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers, res3:res0. equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers, res3:res0. to account for the sign bits of the argu- ments, each argument pairs? most significant bit (msb) is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h 2 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 )
? 2003 microchip technology inc. ds39599c-page 87 pic18f2220/2320/4220/4320 9.0 interrupts the pic18f2320/4320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. high priority interrupt events will interrupt any low priority interrupts that may be in progress. there are ten registers which are used to control interrupt operation. these registers are: rcon intcon intcon2 intcon3 pir1, pir2 pie1, pie2 ipr1, ipr2 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. in general, each interrupt source has three bits to control its operation. the functions of these bits are: flag bit to indicate that an interrupt event occurred enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set priority bit to select high priority or low priority (most interrupt sources have priority bits) the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all inter- rupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vec- tor immediately to address 000008h or 000018h, depending on the priority bit setting. individual inter- rupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in com- patibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit which enables/disables all interrupt sources. all interrupts branch to address 000008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (000008h or 000018h). once in the interrupt service routine, the source(s) of the interrupt can be deter- mined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used) which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior.
pic18f2220/2320/4220/4320 ds39599c-page 88 ? 2003 microchip technology inc. figure 9-1: interrupt logic tmr0ie gieh/gie giel/peie wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip int0if int0ie rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie giel\peie interrupt to cpu vector to location ipen ipe 0018h pspif pspie pspip pspif pspie pspip adif adie adip rcif rcie rcip additional peripheral interrupts adif adie adip high priority interrupt generation low priority interrupt generation rcif rcie rcip additional peripheral interrupts power managed mode
? 2003 microchip technology inc. ds39599c-page 89 pic18f2220/2320/4220/4320 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. register 9-1: intcon register note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif bit 7 bit 0 bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all high priority interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 90 ? 2003 microchip technology inc. register 9-2: intcon2 register r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 u-0 r/w-1 rbpu intedg0 intedg1 intedg2 ?tmr0ip ?rbip bit 7 bit 0 bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 unimplemented: read as ? 0 ? bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 unimplemented: read as ? 0 ? bit 0 rbip: rb port change interrupt priority bit 1 = high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
? 2003 microchip technology inc. ds39599c-page 91 pic18f2220/2320/4220/4320 register 9-3: intcon3 register r/w-1 r/w-1 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 int2ip int1ip ?int2ieint1ie ? int2if int1if bit 7 bit 0 bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 unimplemented: read as ? 0 ? bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling.
pic18f2220/2320/4220/4320 ds39599c-page 92 ? 2003 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are two peripheral interrupt flag registers (pir1, pir2). register 9-4: pir1: peripheral interrupt request (flag) register 1 note 1: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). 2: user software should ensure the appropri- ate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 bit 7 pspif (1) : parallel slave port read/write interrupt flag bit 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred note 1: this bit is reserved on pic18f2x20 devices; always maintain this bit clear. bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rcif: usart receive interrupt flag bit 1 = the usart receive buffer, rcreg, is full (cleared when rcreg is read) 0 = the usart receive buffer is empty bit 4 txif: usart transmit interrupt flag bit 1 = the usart transmit buffer, txreg, is empty (cleared when txreg is written) 0 = the usart transmit buffer is full bit 3 sspif: master synchronous serial port interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: ccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 93 pic18f2220/2320/4220/4320 register 9-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfif cmif ? eeif bclif lvdif tmr3if ccp2if bit 7 bit 0 bit 7 oscfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = system clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5 unimplemented: read as ? 0 ? bit 4 eeif: data eeprom/flash write operation interrupt flag bit 1 = the write operation is complete (must be cleared in software) 0 = the write operation is not complete, or has not been started bit 3 bclif: bus collision interrupt flag bit 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 lvdif: low-voltage detect interrupt flag bit 1 = a low-voltage condition occurred (must be cleared in software) 0 = the device voltage is above the low-voltage detect trip point bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: ccpx interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 94 ? 2003 microchip technology inc. 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of periph- eral interrupt sources, there are two peripheral inter- rupt enable registers (pie1, pie2). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-6: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 bit 7 pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt note 1: this bit is reserved on pic18f2x20 devices; always maintain this bit clear. bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d interrupt 0 = disables the a/d interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie: master synchronous serial port interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the tmr2 to pr2 match interrupt 0 = disables the tmr2 to pr2 match interrupt bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enables the tmr1 overflow interrupt 0 = disables the tmr1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 95 pic18f2220/2320/4220/4320 register 9-7: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 oscfie cmie ? eeie bclie lvdie tmr3ie ccp2ie bit 7 bit 0 bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 =disabled bit 5 unimplemented: read as ? 0 ? bit 4 eeie: data eeprom/flash write operation interrupt enable bit 1 = enabled 0 =disabled bit 3 bclie: bus collision interrupt enable bit 1 = enabled 0 =disabled bit 2 lvdie: low-voltage detect interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp2ie: ccp2 interrupt enable bit 1 = enabled 0 =disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 96 ? 2003 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of periph- eral interrupt sources, there are two peripheral inter- rupt priority registers (ipr1, ipr2). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-8: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip bit 7 bit 0 bit 7 pspip (1) : parallel slave port read/write interrupt priority bit 1 =high priority 0 = low priority note 1: this bit is reserved on pic18f2x20 devices; always maintain this bit set. bit 6 adip: a/d converter interrupt priority bit 1 =high priority 0 = low priority bit 5 rcip: usart receive interrupt priority bit 1 =high priority 0 = low priority bit 4 txip: usart transmit interrupt priority bit 1 =high priority 0 = low priority bit 3 sspip: master synchronous serial port interrupt priority bit 1 =high priority 0 = low priority bit 2 ccp1ip: ccp1 interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 =high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 97 pic18f2220/2320/4220/4320 register 9-9: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 oscfip cmip ? eeip bclip lvdip tmr3ip ccp2ip bit 7 bit 0 bit 7 oscfip: oscillator fail interrupt priority bit 1 =high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 =high priority 0 = low priority bit 5 unimplemented: read as ? 0 ? bit 4 eeip: data eeprom/flash write operation interrupt priority bit 1 =high priority 0 = low priority bit 3 bclip: bus collision interrupt priority bit 1 =high priority 0 = low priority bit 2 lvdip: low-voltage detect interrupt priority bit 1 =high priority 0 = low priority bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 =high priority 0 = low priority bit 0 ccp2ip: ccp2 interrupt priority bit 1 =high priority 0 = low priority legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 98 ? 2003 microchip technology inc. 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from power man- aged mode. rcon also contains the bit that enables interrupt priorities (ipen). register 9-10: rcon register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = cleared by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 99 pic18f2220/2320/4220/4320 9.6 intn pin interrupts external interrupts on the rb0/int0, rb1/int1 and rb2/int2 pins are edge triggered: either rising if the corresponding intedgx bit is set in the intcon2 reg- ister, or falling if the intedgx bit is clear. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxf, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxe. flag bit, intxf, must be cleared in software in the interrupt ser- vice routine before re-enabling the interrupt. all exter- nal interrupts (int0, int1 and int2) can wake-up the processor from the power managed modes if bit intxe was set prior to going into power managed modes. if the global interrupt enable bit gie is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1 and int2 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>) and int2ip (intcon3<7>). there is no priority bit associated with int0. it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow (ffh 00h) in the tmr0 register will set flag bit tmr0if. in 16-bit mode, an overflow (ffffh 0000h) in the tmr0h:tmr0l registers will set flag bit tmr0if. the interrupt can be enabled/disabled by setting/clear- ing enable bit, tmr0ie (intcon<5>). interrupt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?fast register stack? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service rou- tine. depending on the user?s a pplication, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status
pic18f2220/2320/4220/4320 ds39599c-page 100 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 101 pic18f2220/2320/4220/4320 10.0 i/o ports depending on the device selected and features enabled, there are up to five ports available. some pins of the i/o ports are multiplexed with an alternate func- tion from the peripheral features on the device. in gen- eral, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: tris register (data direction register) port register (reads the levels on the pins of the device) lat register (data latch) the data latch (lat register) is useful for read-modify- write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port without the interfaces to other peripherals is shown in figure 10-1. figure 10-1: generic i/o port operation 10.1 porta, trisa and lata registers porta is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input and one of the comparator outputs to become the ra4/t0cki/c1out pin. pins ra6 and ra7 are multiplexed with the main oscillator pins; they are enabled as oscillator or i/o pins by the selection of the main oscillator in configuration register 1h (see section 23.1 ?configuration bits? for details). when they are not used as port pins, ra6 and ra7 and their associated tris and lat bits are read as ? 0 ?. the other porta pins are multiplexed with analog inputs, the analog v ref + and v ref - inputs and the com- parator voltage reference output. the operation of pins, ra3:ra0 and ra5, as a/d converter inputs is selected by clearing/setting the control bits in the adcon1 reg- ister (a/d control register 1). pins ra0 through ra5 may also be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. the ra4/t0cki/c1out pin is a schmitt trigger input and an open-drain output. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the ra pins even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. example 10-1: initializing porta data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . note: on a power-on reset, ra5 and ra3:ra0 are configured as analog inputs and read as ? 0 ?. ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 0x07 ; configure a/d movwf adcon1 ; for digital inputs movlw 0xcf ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs
pic18f2220/2320/4220/4320 ds39599c-page 102 ? 2003 microchip technology inc. figure 10-2: block diagram of ra3:ra0 and ra5 pins figure 10-3: block diagram of ra6 pin figure 10-4: block diagram of ra4/t0cki pin figure 10-5: block diagram of ra7 pin data bus qd en p n wr lata wr trisa data latch tris latch rd trisa rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . analog input mode ttl input buffer to a/d converter and lvd modules rd lata or porta q d q ck q d q ck ss input (ra5 only) data bus q d q ck qd en p n wr lata wr data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata ra6 enable ecio or enable ttl input buffer rcio trisa q d q ck trisa data bus wr trisa rd porta data latch tris latch schmitt trigger input buffer n v ss i/o pin (1) tmr0 clock input q d q ck q d q ck en qd en rd lata wr lata or porta note 1: i/o pins have protection diodes to v dd and v ss . rd trisa data bus q d q ck qd en p n wr lata wr data latch tris latch rd rd porta v ss v dd i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . or porta rd lata enable ttl input buffer ra7 trisa q d q ck trisa ra7 enable to oscillator
? 2003 microchip technology inc. ds39599c-page 103 pic18f2220/2320/4220/4320 table 10-1: porta functions table 10-2: summary of registers associated with porta name bit# buffer function ra0/an0 bit 0 ttl input/output or analog input. ra1/an1 bit 1 ttl input/output or analog input. ra2/an2/v ref -/cv ref bit 2 ttl input/output, analog input, v ref - or comparator v ref output. ra3/an3/v ref + bit 3 ttl input/output, analog input or v ref +. ra4/t0cki/c1out bit 4 st input/output, external clock input for timer0 or comparator 1 output. output is open-drain type. ra5/an4/ss /lvdin/c2out bit 5 ttl input/output, analog input, slave select input for synchronous serial port, low-voltage detect input or comparator 2 output. osc2/clko/ra6 bit 6 ttl osc2, clock output or i/o pin. osc1/clki/ra7 bit 7 ttl osc1, clock input or i/o pin. legend: ttl = ttl input, st = schmitt trigger input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 uu0u 0000 lata lata7 (1) lata6 (1) lata data latch register xxxx xxxx uuuu uuuu trisa trisa7 (1) trisa6 (1) porta data direction register 1111 1111 1111 1111 adcon1 ? ? vcfg1 vcfg0pcfg3pcfg2pcfg1pcfg0 --00 0000 --00 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: ra7:ra6 and their associated latch and data direction bits are enabled as i/o pins based on oscillator configuration; otherwise, they are read as ? 0 ?.
pic18f2220/2320/4220/4320 ds39599c-page 104 ? 2003 microchip technology inc. 10.2 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 10-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is per- formed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt- on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt- on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are or?ed together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff (any), portb instruction). this will end the mismatch condition. b) clear flag bit rbif. a mismatch condition will continue to set flag bit rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. rb3 can be configured by the configuration bit, ccp2mx, as the alternate peripheral pin for the ccp2 module (ccp2mx = 0 ). figure 10-6: block diagram of rb7:rb5 pins note: on a power-on reset, rb4:rb0 are con- figured as analog inputs by default and read as ? 0 ?; rb7:rb5 are configured as digital inputs. by programming the configuration bit, pbaden (config3h<1>), rb4:rb0 will alternatively be configured as digital inputs on por. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0x0f ; set rb<4:0> as movwf adcon1 ; digital i/o pins ; (required if config bit ; pbaden is set) movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs data latch from other rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb rb7:rb5 and weak pull-up rd portb latch ttl input buffer st buffer rb7:rb5 in serial programming mode q3 q1 rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). rb4 pins
? 2003 microchip technology inc. ds39599c-page 105 pic18f2220/2320/4220/4320 figure 10-7: block diagram of rb2:rb0 pins figure 10-8: block diagram of rb4 pin figure 10-9: block diag ram of rb3/ccp2 pin data latch rbpu (2) p v dd data bus wr latb wr trisb rd trisb rd portb weak pull-up intx i/o pin (1) schmitt trigger buffer tris latch rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). to a/d converter analog input mode ttl input buffer q d ck q d ck en qd en data latch from rb7:rb5 rbpu (2) p v dd i/o pin (1) q d ck q d ck qd en qd en data bus wr latb wr trisb set rbif tris latch rd trisb rd portb weak pull-up rd portb latch ttl input buffer q3 q1 rd latb or portb note 1: i/o pins have diode protection to v dd and v ss . 2: to enable weak pull-ups, set the appropriate tris bit(s) and clear the rbpu bit (intcon2<7>). to a/d converter port/ccp2 select data bus wr latb wr trisb data latch tris latch rd trisc ccp2 d ata out 0 1 p n v dd v ss rd portb ccp2 input rb3 pin (1) or portb rd latc schmitt trigger note 1: i/o pins have diode protection to v dd and v ss . v dd weak pull-up p rbpu ttl input buffer analog input mode analog input mode to a/d converter q d ck en qd en q d ck
pic18f2220/2320/4220/4320 ds39599c-page 106 ? 2003 microchip technology inc. table 10-3: portb functions table 10-4: summary of registers associated with portb name bit# buffer function rb0/an12/int0 bit 0 ttl (1) /st (2) input/output pin, analog input or external interrupt input 0. internal software programmable weak pull-up. rb1/an10/int1 bit 1 ttl (1) /st (2) input/output pin, analog input or external interrupt input 1. internal software programmable weak pull-up. rb2/an8/int2 bit 2 ttl (1) /st (2) input/output pin, analog input or external interrupt input 2. internal software programmable weak pull-up. rb3/an9/ccp2 bit 3 ttl (1) /st (3) input/output pin or analog input. capture2 input/compare2 output/ pwm output when ccp2mx configuration bit is set (4) . internal software programmable weak pull-up. rb4/an11/kbi0 bit 4 ttl input/output pin (with interrupt-on-change) or analog input. internal software programmable weak pull-up. rb5/kbi1/pgm bit 5 ttl/st (5) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. low-voltage icsp enable pin. rb6/kbi2/pgc bit 6 ttl/st (5) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming clock. rb7/kbi3/pgd bit 7 ttl/st (5) input/output pin (with interrupt-on-change). internal software programmable weak pull-up. serial programming data. legend: ttl = ttl input, st = schmitt trigger input note 1: this buffer is a ttl input when configured as digital i/o. 2: this buffer is a schmitt trigger input when configured as the external interrupt. 3: this buffer is a schmitt trigger input when configured as the ccp2 input. 4: a device configuration bit selects which i/o pin the ccp2 pin is multiplexed on. 5: this buffer is a schmitt trigger input when used in serial programming mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxq qqqq uuuu uuuu latb latb data latch register xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u intcon2 rbpu intedg0 intedg1 intedg2 ? tmr0ip ?rbip 1111 -1-1 1111 -1-1 intcon3 int2ip int1ip ? int2ie int1ie ? int2if int1if 11-0 0-00 11-0 0-00 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, q = value depends on condition. shaded cells are not used by portb.
? 2003 microchip technology inc. ds39599c-page 107 pic18f2220/2320/4220/4320 10.3 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 10-5). the pins have schmitt trigger input buff- ers. rc1 is normally configured by configuration bit, ccp2mx (config3h<0>), as the default peripheral pin of the ccp2 module (default/erased state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents even though a peripheral device may be overriding one or more of the pins. example 10-3: initializing portc figure 10-10: portc block diagram (peripheral output override) note: on a power-on reset, these pins are configured as digital inputs. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs data bus wr latc or wr trisc rd trisc peripheral data out 0 1 rd portc peripheral data in wr portc rd latc peripheral output schmitt port/peripheral select (2) enable (3) p n v ss v dd i/o pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: port/peripheral select signal selects between port data (output) and peripheral output. 3: peripheral output enable is only active if peripheral select is active. data latch tris latch trigger q d q ck q d q ck q d en
pic18f2220/2320/4220/4320 ds39599c-page 108 ? 2003 microchip technology inc. table 10-5: portc functions table 10-6: summary of registers associated with portc name bit# buffer type function rc0/t1oso/t1cki bit 0 st input/output port pin or timer1 oscillator output/timer1 clock input. rc1/t1osi/ccp2 bit 1 st input/output port pin, timer1 oscillator input or capture2 input/ compare2 output/pwm output when ccp2mx configuration bit is disabled. rc2/ccp1/p1a (1) bit 2 st input/output port pin, capture1 input/compare1 output/pwm1 output or enhanced pwm output a (1) . rc3/sck/scl bit 3 st rc3 can also be the synchronous serial clock for both spi and i 2 c modes. rc4/sdi/sda bit 4 st rc4 can also be the spi data in (spi mode) or data i/o (i 2 c mode). rc5/sdo bit 5 st input/output port pin or synchronous serial port data output. rc6/tx/ck bit 6 st input/output port pin, addressable usart asynchronous transmit or addressable usart synchronous clock. rc7/rx/dt bit 7 st input/output port pin, addressable usart asynchronous receive or addressable usart synchronous data. legend: st = schmitt trigger input note 1: enhanced pwm output is available only on pic18f4x20 devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu latc latc data latch register xxxx xxxx uuuu uuuu trisc portc data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged
? 2003 microchip technology inc. ds39599c-page 109 pic18f2220/2320/4220/4320 10.4 portd, trisd and latd registers portd is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register read and write the latched output value for portd. all pins on portd are implemented with schmitt trig- ger input buffers. each pin is individually configurable as an input or output. three of the portd pins are multiplexed with outputs p1b, p1c and p1d of the enhanced ccp module. the operation of these additional pwm output pins is covered in greater detail in section 16.0 ?enhanced capture/compare/pwm (eccp) module? . portd can also be configured as an 8-bit wide micro- processor port (parallel slave port) by setting control bit, pspmode (trise<4>). in this mode, the input buffers are ttl. see section 10.6 ?parallel slave port? for additional information on the parallel slave port (psp). example 10-4: initializing portd figure 10-11: block diagram of rd7:rd5 pins note: portd is only available on pic18f4x20 devices. note: on a power-on reset, these pins are configured as digital inputs. note: when the enhanced pwm mode is used with either dual or quad outputs, the psp functions of portd are automatically disabled. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0xcf ; value used to ; initialize data ; direction movwf trisd : set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs data bus wr latd wr trisd data latch tris latch rd trisd i/o pin (1) q d ck q d ck en qd en rd latd or portd 0 1 0 1 q q 0 1 p n v dd v ss 0 1 rd portd psp write psp read note 1: i/o pins have diode protection to v dd and v ss . ttl buffer schmitt trigger input buffer portd/ccp1 select ccp data out pspmode
pic18f2220/2320/4220/4320 ds39599c-page 110 ? 2003 microchip technology inc. figure 10-12: block diagram of rd4:rd0 pins table 10-7: portd functions table 10-8: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit 0 st/ttl (1) input/output port pin or parallel slave port bit 0. rd1/psp1 bit 1 st/ttl (1) input/output port pin or parallel slave port bit 1. rd2/psp2 bit 2 st/ttl (1) input/output port pin or parallel slave port bit 2. rd3/psp3 bit 3 st/ttl (1) input/output port pin or parallel slave port bit 3. rd4/psp4 bit 4 st/ttl (1) input/output port pin or parallel slave port bit 4. rd5/psp5/p1b bit 5 st/ttl (1) input/output port pin, parallel slave port bit 5 or enhanced pwm output p1b. rd6/psp6/p1c bit 6 st/ttl (1) input/output port pin, parallel slave port bit 6 or enhanced pwm output p1c. rd7/psp7/p1d bit 7 st/ttl (1) input/output port pin, parallel slave port bit 7 or enhanced pwm output p1d. legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu latd latd data latch register xxxx xxxx uuuu uuuu trisd portd data direction register 1111 1111 1111 1111 trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by portd. data bus wr latd wr trisd data latch tris latch rd trisd i/o pin (1) q d ck q d ck en qd en rd latd or portd 0 1 q q 0 1 p n v dd v ss 0 1 rd portd psp write psp read note 1: i/o pins have diode protection to v dd and v ss . ttl buffer schmitt trigger input buffer portd/ccp1 select pspmode
? 2003 microchip technology inc. ds39599c-page 111 pic18f2220/2320/4220/4320 10.5 porte, trise and late registers depending on the particular pic18f2x20/4x20 device selected, porte is implemented in two different ways. for pic18f4x20 devices, porte is a 4-bit wide port. three pins (re0/an5/rd , re1/an6/wr and re2/ an7/cs ) are individually configurable as inputs or out- puts. these pins have schmitt trigger input buffers. when selected as an analog input, these pins will read as ? 0 ?s. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). trise controls the direction of the re pins even when they are being used as analog inputs. the user must make sure to keep the pins configured as inputs when using them as analog inputs. the upper four bits of the trise register also control the operation of the parallel slave port. their operation is explained in register 10-1. the data latch register (late) is also memory mapped. read-modify-write operations on the late register read and write the latched output value for porte. the fourth pin of porte (mclr /v pp /re3) is an input only pin. its operation is controlled by the mclre con- figuration bit in configuration register 3h (config3h<7>). when selected as a port pin (mclre = 0 ), it functions as a digital input only pin; as such, it does not have tris or lat bits associated with its operation. otherwise, it functions as the device?s master clear input. in either configuration, re3 also functions as the programming voltage input during programming. example 10-5: initializing porte 10.5.1 porte in 28-pin devices for pic18f2x20 devices, porte is only available when master clear functionality is disabled (config3h<7> = 0 ). in these cases, porte is a single bit, input only port comprised of re3 only. the pin operates as previously described. figure 10-13: block diagram of re2:re0 pins figure 10-14: block diagram of mclr /v pp /re3 pin note: on a power-on reset, re2:re0 are configured as analog inputs. note: on a power-on reset, re3 is enabled as a digital input only if master clear functionality is disabled. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 0x0a ; configure a/d movwf adcon1 ; for digital inputs movlw 0x03 ; value used to ; initialize data ; direction movwf trisc ; set re<0> as inputs ; re<1> as outputs ; re<2> as inputs data bus wr late wr trise rd porte data latch tris latch rd trise schmitt trigger input buffer q d ck q d ck en qd en i/o pin (1) rd late or porte to analog converter note 1: i/o pins have diode protection to v dd and v ss . mclr /v pp / data bus rd porte rd late schmitt trigger mclre rd trise qd en latch filter low-level mclr detect high-voltage detect internal mclr hv re3
pic18f2220/2320/4220/4320 ds39599c-page 112 ? 2003 microchip technology inc. register 10-1: trise register r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode ? trise2 trise1 trise0 bit 7 bit 0 bit 7 ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6 obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov : input buffer overflow detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3 unimplemented: read as ? 0 ? bit 2 trise2 : re2 direction control bit 1 = input 0 = output bit 1 trise1 : re1 direction control bit 1 = input 0 = output bit 0 trise0 : re0 direction control bit 1 = input 0 = output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 113 pic18f2220/2320/4220/4320 table 10-9: porte functions table 10-10: summary of registers associated with porte name bit# buffer type function re0/an5/rd bit 0 st/ttl (1) input/output port pin, analog input or read control input in parallel slave port mode. for rd (psp control mode): 1 = psp is idle 0 = read operation. reads portd register (if chip selected). re1/an6/wr bit 1 st/ttl (1) input/output port pin, analog input or write control input in parallel slave port mode. for wr (psp control mode): 1 = psp is idle 0 = write operation. writes portd register (if chip selected). re2/an7/cs bit 2 st/ttl (1) input/output port pin, analog input or chip select control input in parallel slave port mode. for cs (psp control mode): 1 = psp is idle 0 = external device is selected mclr /v pp /re3 bit 3 st input only port pin or programming voltage input (if mclr is disabled); master clear input or programming voltage input (if mclr is enabled). legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets porte ? ? ? ?re3 (1) re2 re1 re0 ---- q000 ---- q000 late ? ? ? ? ? late data latch register ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition. shaded cells are not used by porte. note 1: implemented only when master clear functionality is disabled (config3h<7> = 0 ).
pic18f2220/2320/4220/4320 ds39599c-page 114 ? 2003 microchip technology inc. 10.6 parallel slave port in addition to its function as a general i/o port, portd can also operate as an 8-bit wide parallel slave port (psp) or microprocessor port. psp operation is con- trolled by the 4 upper bits of the trise register (register 10-1). setting control bit, pspmode (trise<4>), enables psp operation, as long as the enhanced ccp module is not operating in dual output or quad output pwm mode. in slave mode, the port is asynchronously readable and writable by the external world. the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting the control bit, pspmode, enables the porte i/o pins to become control inputs for the microprocessor port. when set, port pin re0 is the rd input, re1 is the wr input and re2 is the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be config- ured as inputs (set). the a/d port configuration bits pfcg3:pfcg0 (adcon1<3:0>) must also be set to ? 1010 ?. a write to the psp occurs when both the cs and wr lines are first detected low and ends when either are detected high. the pspif and ibf flag bits are both set when the write ends. a read from the psp occurs when both the cs and rd lines are first detected low. the data in portd is read out and the obf bit is set. if the user writes new data to portd to set obf, the data is immediately read out; however, the obf bit is not set. when either the cs or rd lines are detected high, the portd pins return to the input state and the pspif bit is set. user applications should wait for pspif to be set before servicing the psp; when this happens, the ibf and obf bits can be polled and the appropriate action taken. the timing for the control signals in write and read modes is shown in figure 10-16 and figure 10-17, respectively. figure 10-15: portd and porte block diagram (parallel slave port) note: the parallel slave port is only available on pic18f4x20 devices. data bus wr latd rdx pin q d ck en qd en rd portd one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr ttl ttl ttl ttl or wr portd rd latd data latch note: i/o pins have diode protection to v dd and v ss . porte pins
? 2003 microchip technology inc. ds39599c-page 115 pic18f2220/2320/4220/4320 figure 10-16: parallel slave port write waveforms figure 10-17: parallel slave port read waveforms table 10-11: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets portd port data latch when written; port pins when read xxxx xxxx uuuu uuuu latd latd data latch bits xxxx xxxx uuuu uuuu trisd portd data direction bits 1111 1111 1111 1111 porte ? ? ? ? re3 re2 re1 re0 ---- 0000 ---- 0000 late ? ? ? ? ? late data latch bits ---- -xxx ---- -uuu trise ibf obf ibov pspmode ? porte data direction bits 0000 -111 0000 -111 intcon gie/ gieh peie/ giel tmr0if int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 --00 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port.
pic18f2220/2320/4220/4320 ds39599c-page 116 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 117 pic18f2220/2320/4220/4320 11.0 timer0 module the timer0 module has the following features: software selectable as an 8-bit or 16-bit timer/counter readable and writable dedicated 8-bit software programmable prescaler clock source selectable to be external or internal interrupt-on-overflow from ffh to 00h in 8-bit mode and ffffh to 0000h in 16-bit mode edge select for external clock figure 11-1 shows a simplified block diagram of the timer0 module in 8-bit mode and figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. the t0con register (register 11-1) is a readable and writable register that controls all the aspects of timer0, including the prescale selection. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit: timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0: timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 118 ? 2003 microchip technology inc. figure 11-1: timer0 block diagram in 8-bit mode figure 11-2: timer0 block diagram in 16-bit mode note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki maximum prescale. ra4/t0cki/c1out t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 (2 t cy delay) data bus 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 pin note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki maximum prescale. t0se 0 1 0 1 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) data bus<7:0> 8 psa t0ps2, t0ps1, t0ps0 set interrupt flag bit tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l ra4/t0cki/c1out pin
? 2003 microchip technology inc. ds39599c-page 119 pic18f2220/2320/4220/4320 11.1 timer0 operation timer0 can operate as a timer or as a counter. timer mode is selected by clearing the t0cs bit. in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if the tmr0 regis- ter is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit. in counter mode, timer0 will increment, either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit (t0se). clearing the t0se bit selects the rising edge. when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 11.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not readable or writable. the psa and t0ps2:t0ps0 bits determine the prescaler assignment and prescale ratio. clearing bit psa will assign the prescaler to the timer0 module. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0, movwf tmr0, bsf tmr0, x ....etc.) will clear the prescaler count. 11.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during program execution). 11.3 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if bit. the interrupt can be masked by clearing the tmr0ie bit. the tmr0if bit must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the tmr0 interrupt cannot awaken the processor from sleep mode, since the timer requires clock cycles, even when t0cs is set. 11.4 16-bit mode timer reads and writes tmr0h is not the high byte of the timer/counter in 16-bit mode but is actually a buffered version of the high byte of timer0 (refer to figure 11-2). the high byte of the timer0 counter/timer is not directly readable nor writable. tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this pro- vides the ability to read all 16 bits of timer0, without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. a write to the high byte of timer0 must also take place through the tmr0h buffer register. timer0 high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets tmr0l timer0 module low byte register xxxx xxxx uuuu uuuu tmr0h timer0 module high byte register 0000 0000 0000 0000 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 1111 1111 trisa ra7 (1) ra6 (1) porta data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by timer0. note 1: ra6 and ra7 are enabled as i/o pins depending on the oscillator mode selected in configuration word 1h.
pic18f2220/2320/4220/4320 ds39599c-page 120 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 121 pic18f2220/2320/4220/4320 12.0 timer1 module the timer1 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr1h and tmr1l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from ccp module special event trigger status of system clock operation figure 12-1 is a simplified block diagram of the timer1 module. register 12-1 details the timer1 control register. this register controls the operating mode of the timer1 module and contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). the timer1 oscillator can be used as a secondary clock source in power managed modes. when the t1run bit is set, the timer1 oscillator is providing the system clock. if the fail-safe clock monitor is enabled and the timer1 oscillator fails while providing the system clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. register 12-1: t1con: timer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = system clock is derived from timer1 oscillator 0 = system clock is derived from another source bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut-off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 (external clock): 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 (internal clock): this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from pin rc0/t1oso/t13cki (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 122 ? 2003 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs = 0 , timer1 increments every instruc- tion cycle. when tmr1cs = 1 , timer1 increments on every rising edge of the external clock input, or the timer1 oscillator, if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. the trisc1:trisc0 values are ignored and the pins read as ? 0 ?. timer1 also has an internal ?reset input?. this reset can be generated by the ccp module (see section 15.4.4 ?special event trigger? ). figure 12-1: timer1 block diagram figure 12-2: timer1 block diag ram: 16-bit read/write mode t1osc tmr1h tmr1l t1sync tmr1cs t1ckps1:t1ckps0 peripheral clocks f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 tmr1if overflow tmr1 clr ccp special event trigger t1oscen enable oscillator (1) interrupt flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. th is eliminates power drain. t1osi t1cki/t1oso timer 1 tmr1l t1osc t1sync tmr1cs t1ckps1:t1ckps0 peripheral clocks t1oscen enable oscillator (1) tmr1if overflow interrupt f osc /4 internal clock tmr1on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1cki/t1oso t1osi tmr1 flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr1h 8 8 8 read tmr1l write tmr1l clr ccp special event trigger
? 2003 microchip technology inc. ds39599c-page 123 pic18f2220/2320/4220/4320 12.2 timer1 oscillator a crystal oscillator circuit is built-in between pins, t1osi (input) and t1oso (amplifier output). it is enabled by setting control bit, t1oscen (t1con<3>). the oscillator is a low-power oscillator rated for 32 khz crystals. it will continue to run during all power man- aged modes. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 lp oscillator table 12-1: capacitor selection for the timer oscillator (2,3,4) 12.3 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the ccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4, may be helpful when used on a single-sided pcb or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring osc type freq c1 c2 lp 32 khz 27 pf (1) 27 pf (1) note 1: microchip suggests this value as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. note: see the notes with table 12-1 for additiona l information about capacitor selection. c1 c2 xtal pic18fxxxx t1osi t1oso 32.768 khz 33 pf 33 pf v dd osc1 v ss osc2 rc0 rc1 rc2 note: not drawn to scale.
pic18f2220/2320/4220/4320 ds39599c-page 124 ? 2003 microchip technology inc. 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled/disabled by setting/clearing timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer1 and start an a/d conversion if the a/d module is enabled (see section 15.4.4 ?special event trigger? for more information). timer1 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer1. 12.6 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writ- able in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 12.7 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.2 ?timer1 oscillator? above), gives users the option to include rtc function- ality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 reg- ister pair to overflow, triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it; the simplest method is to set the msbit of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ) as shown in the rou- tine, rtcinit . the timer1 oscillator must also be enabled and running at all times. note: the special event triggers from the ccp1 module will not set interrupt flag bit, tmr1if (pir1<0>).
? 2003 microchip technology inc. ds39599c-page 125 pic18f2220/2320/4220/4320 example 12-1: implementing a real-time clock using a timer1 interrupt service table 12-2: registers associated with timer1 as a timer/counter rtcinit movlw 0x80 ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1osc ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h,7 ; preload for 1 sec overflow bcf pir1,tmr1if ; clear interrupt flag incf secs,f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins,f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours,f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done movlw .01 ; reset hours to 1 movwf hours return ; done name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 u0uu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 126 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 127 pic18f2220/2320/4220/4320 13.0 timer2 module the timer2 module timer has the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16) interrupt on tmr2 match with pr2 ssp module optional use of tmr2 output to generate clock shift timer2 has a control register shown in register 13-1. tmr2 can be shut-off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. figure 13-1 is a simplified block diagram of the timer2 module. register 13-1 shows the timer2 control regis- ter. the prescaler and postscaler selection of timer2 are controlled by this register. 13.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the ccp module. the tmr2 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, t2ckps1:t2ckps0 (t2con<1:0>). the match out- put of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit, tmr2if (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: timer2 contro l register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps3:toutps0: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 128 ? 2003 microchip technology inc. 13.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. 13.3 output of tmr2 the output of tmr2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock. figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter comparator tmr2 sets flag tmr2 output (1) reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if note 1: tmr2 register output can be software selected by the ssp module as a baud clock. toutps3:toutps0 t2ckps1:t2ckps0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 pr2 timer2 period register 1111 1111 1111 1111 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 qq00 0000 qq00 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x2 devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39599c-page 129 pic18f2220/2320/4220/4320 14.0 timer3 module the timer3 module timer/counter has the following features: 16-bit timer/counter (two 8-bit registers: tmr3h and tmr3l) readable and writable (both registers) internal or external clock select interrupt-on-overflow from ffffh to 0000h reset from ccp module trigger figure 14-1 is a simplified block diagram of the timer3 module. register 14-1 shows the timer3 control register. this register controls the operating mode of the timer3 module and sets the ccp clock source. register 12-1 shows the timer1 control register. this register controls the operating mode of the timer1 module, as well as contains the timer1 oscillator enable bit (t1oscen) which can be a clock source for timer3. register 14-1: t3con: time r3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on bit 7 bit 0 bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6, 3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 1x = timer3 is the clock source for compare/capture ccp modules 01 = timer3 is the clock source for compare/capture of ccp2, timer1 is the clock source for compare/capture of ccp1 00 = timer1 is the clock source for compare/capture ccp modules bit 5-4 t3ckps1:t3ckps0: timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t3sync : timer3 external clock input synchronization control bit (not usable if the system clock comes from timer1/timer3.) when tmr3cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr3cs = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t1cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 130 ? 2003 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of these modes: as a timer as a synchronous counter as an asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs = 0 , timer3 increments every instruc- tion cycle. when tmr3cs = 1 , timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator if enabled. when the timer1 oscillator is enabled (t1oscen is set), the rc1/t1osi/ccp2 and rc0/t1oso/t1cki pins become inputs. that is, the trisc1:trisc0 value is ignored and the pins are read as ? 0 ?. timer3 also has an internal ?reset input?. this reset can be generated by the ccp module (see section 15.4.4 ?special event trigger? ). figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram co nfigured in 16-bit read/write mode tmr3h tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 peripheral clocks t1oscen enable oscillator (1) tmr3if overflow interrupt f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi flag bit note 1: when enable bit t1oscen is cleared, the inverter and feedback resistor are turned off. th is eliminates power drain. t1cki clr ccp special event trigger t3ccpx timer3 tmr3l t1osc t3sync tmr3cs t3ckps1:t3ckps0 peripheral clocks t1oscen enable oscillator (1) f osc /4 internal clock tmr3on on/off prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 t1oso/ t1osi tmr3 t1cki clr ccp special event trigger t3ccpx to timer1 clock input note 1: when the t1oscen bit is cleared, the inverter and feedback re sistor are turned off. this eliminates power drain. high byte data bus<7:0> 8 tmr3h 8 8 8 read tmr3l write tmr3l set tmr3if flag bit on overflow
? 2003 microchip technology inc. ds39599c-page 131 pic18f2220/2320/4220/4320 14.2 timer1 oscillator the timer1 oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. the oscillator is a low- power oscillator rated for 32 khz crystals. see section 12.2 ?timer1 oscillator? for further details. 14.3 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and rolls over to 0000h. the tmr3 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled/disabled by setting/clearing tmr3 interrupt enable bit, tmr3ie (pie2<1>). 14.4 resetting timer3 using a ccp trigger output if the ccp module is configured in compare mode to generate a ?special event trigger? (ccp1m3:ccp1m0 = 1011 ), this signal will reset timer3. see section 15.4.4 ?special event trigger? for more information. timer3 must be configured for either timer or synchro- nized counter mode to take advantage of this feature. if timer3 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from ccp1, the write will take precedence. in this mode of operation, the ccpr1h:ccpr1l register pair effectively becomes the period register for timer3. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the ccp module will not set interrupt flag bit, tmr3if (pir1<0>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir2 oscif cmif ? eeif bclif lvdif tmr3if ccp2if 00-0 0000 00-0 0000 pie2 oscie cmie ? eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 00-0 0000 ipr2 oscip cmip ? eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 11-1 1111 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 u0uu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the timer3 module.
pic18f2220/2320/4220/4320 ds39599c-page 132 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 133 pic18f2220/2320/4220/4320 15.0 capture/compare/pwm (ccp) modules the standard ccp (capture/compare/pwm) module contains a 16-bit register that can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. table 15-1 shows the timer resources required for each of the ccp module modes. the operation of ccp1 is identical to that of ccp2, with the exception of the special event trigger. therefore, operation of a ccp module is described with respect to ccp1 except where noted. table 15-2 shows the interaction of the ccp modules. register 15-1: ccpxcon: ccp module contro l register note: in 28-pin devices, both ccp1 and ccp2 function as standard ccp modules. in 40-pin devices, ccp1 is implemented as an enhanced ccp module, offering addi- tional capabilities in pwm mode. capture and compare modes are identical in all modules regardless of the device. please see section 16.0 ?enhanced capture/compare/pwm (eccp) mod- ule? for a discussion of the enhanced pwm capabilities of the ccp1 module. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 bit 7-6 reserved: read as ? 0 ?. see section 16.0 ?enhanced capture/compare/pwm (eccp) module? . bit 5-4 dcxb1:dcxb0: pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs (bit 1 and bit 0) of the 10-bit pwm duty cycle. the upper eight bits (dcx9:dcx2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode, toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, initialize ccp pin low; on compare match, force ccp pin high (ccpxif bit is set) 1001 = compare mode, initialize ccp pin high; on compare match, force ccp pin low (ccpxif bit is set) 1010 = compare mode, generate software interrupt on compare match (ccpxif bit is set, ccp pin operates as a port pin for input and output) 1011 = compare mode, trigger special event (ccp2if bit is set) 11xx =pwm mode legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 134 ? 2003 microchip technology inc. 15.1 ccp1 module capture/compare/pwm register 1 (ccpr1) is com- prised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp1. all are readable and writable. table 15-1: ccp mode - timer resource 15.2 ccp2 module capture/compare/pwm register 2 (ccpr2) is com- prised of two 8-bit registers: ccpr2l (low byte) and ccpr2h (high byte). the ccp2con register controls the operation of ccp2. all are readable and writable. ccp2 functions identically to ccp1 except for the enhanced pwm modes offered by ccp2 table 15-2: interaction of two ccp modules ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 ccpx mode ccpy mode interaction capture capture tmr1 or tmr3 time base. time base can be different for each ccp. capture compare the compare could be configured for the special event trigger which clears either tmr1 or tmr3 depending upon which time base is used. compare compare the compare(s) could be configured for the special event trigger which clears tmr1 or tmr3 depending upon which time base is used. pwm pwm the pwms will have the same frequency and update rate (tmr2 interrupt). pwm capture none. pwm compare none.
? 2003 microchip technology inc. ds39599c-page 135 pic18f2220/2320/4220/4320 15.3 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on pin rc2/ccp1/p1a. an event is defined as one of the following: every falling edge every rising edge every 4th rising edge every 16th rising edge the event is selected by control bits, ccp1m3:ccp1m0 (ccp1con<3:0>). when a capture is made, the inter- rupt request flag bit, ccp1if (pir1<2>), is set; it must be cleared in software. if anot her capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 15.3.1 ccp pin configuration in capture mode, the rc2/ccp1/p1a pin should be configured as an input by setting the trisc<2> bit. 15.3.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (either timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchro- nous counter mode, the capture operation may not work. the timer to be used with each ccp module is selected in the t3con register. 15.3.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<2>) clear to avoid false interrupts and should clear the flag bit, ccp1if, following any such change in operating mode. 15.3.4 ccp prescaler there are four prescaler settings specified by bits ccp1m3:ccp1m0. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 15-1 shows the recom- mended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 15-1: changing between capture prescalers figure 15-1: capture mode operat ion block diagram note: if the rc2/ccp1/p1a is configured as an output, a write to the port can cause a capture condition. clrf ccp1con, f ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp1con ; load ccp1con with ; this value ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if tmr3 enable q?s ccp1con<3:0> ccp1 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp2 ccpr2h ccpr2l tmr1h tmr1l set flag bit ccp2if tmr3 enable q?s ccp2con<3:0> ccp2 pin prescaler 1, 4, 16 and edge detect tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1
pic18f2220/2320/4220/4320 ds39599c-page 136 ? 2003 microchip technology inc. 15.4 compare mode in compare mode, the 16-bit ccpr1 (ccpr2) register value is constantly compared against either the tmr1 register pair value, or the tmr3 register pair value. when a match occurs, the rc2/ccp1/p1a (rc1/t1osi/ccp2) pin: is driven high is driven low toggles output (high to low or low to high) remains unchanged (interrupt only) the action on the pin is based on the value of control bits, ccp1m3:ccp1m0 (ccp2m3:ccp2m0). at the same time, interrupt flag bit, ccp1if (ccp2if), is set. 15.4.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate trisc bit. 15.4.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode, or synchronized counter mode, if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 15.4.3 software interrupt mode when generate software interrupt is chosen, the ccp1 pin is not affected. only a ccp interrupt is generated (if enabled). 15.4.4 special event trigger in this mode, an internal hardware trigger is generated which may be used to initiate an action. the special event trigger output of ccp1 resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special trigger output of ccp2 resets either the tmr1 or tmr3 register pair. additionally, the ccp2 special event trigger will start an a/d conversion if the a/d module is enabled. figure 15-2: compare mode operation block diagram note: clearing the ccp1con register will force the rc2/ccp1/p1a compare output latch to the default low level. this is not the portc i/o data latch. note: the special event trigger from the ccp2 module will not set the timer1 or timer3 interrupt flag bits. ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if match rc2/ccp1/p1a trisc<2> ccp1con<3:0> mode select output enable special event trigger will: reset timer1 or timer3 but not set timer1 or timer3 interrupt flag bit and set bit go/done (adcon0<2>) which starts an a/d conversion (ccp2 only) tmr3h tmr3l t3ccp2 ccpr2h ccpr2l comparator 1 0 t3ccp2 t3ccp1 qs r output logic special event trigger set flag bit ccp2if match rc1/t1osi/ccp2 trisc<1> ccp2con<3:0> mode select output enable 01 pin pin
? 2003 microchip technology inc. ds39599c-page 137 pic18f2220/2320/4220/4320 table 15-3: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 pir2 oscfif cmif ? eeif bclif lvdif tmr3if ccp2if 00-0 0000 00-0 0000 pie2 oscfie cmie ? eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 00-0 0000 ipr2 oscfip cmip ? eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 11-1 1111 tmr3l holding register for the least significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu tmr3h holding register for the most significant byte of the 16-bit tmr3 register xxxx xxxx uuuu uuuu t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 uuuu uuuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by capture and timer1. note 1: these bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 138 ? 2003 microchip technology inc. 15.5 pwm mode in pulse width modulation (pwm) mode, the ccp1 pin produces up to a 10-bit resolution pwm output. since the ccp1 pin is multiplexed with the portc data latch, the trisc<2> bit must be cleared to make the ccp1 pin an output. figure 15-3 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up the ccp module for pwm operation, see section 15.5.3 ?setup for pwm operation? . figure 15-3: simplified pwm block diagram a pwm output (figure 15-4) has a time base ( period ) and a time that the output is high ( duty cycle ). the frequency of the pwm is the inverse of the period (1/period). figure 15-4: pwm output 15.5.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following equation. equation 15-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the ccp1 pin is set (if pwm duty cycle = 0%, the ccp1 pin will not be set) the pwm duty cycle is copied from ccpr1l into ccpr1h 15.5.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccpr1l:ccp1con<5:4>. the pwm duty cycle is calculated by the following equation. equation 15-2: ccpr1l and ccp1con<5:4> can be written to at any time but the duty cycle value is not copied into ccpr1h until a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. note: clearing the ccp1con register will force the ccp1 pwm output latch to the default low level. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) r q s duty cycle registers ccp1con<5:4> clear timer, ccp1 pin and latch d.c. trisc<2> rc2/ccp1/p1a note: 8-bit timer is concatenated with 2-bit internal q clock or 2 bits of the prescaler to create 10-bit time base. period duty cycle tmr2 = pr2 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 13.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] 4 t osc (tmr2 prescale value) pwm duty cycle = (ccpr1l:ccp1con<5:4>) t osc (tmr2 prescale value)
? 2003 microchip technology inc. ds39599c-page 139 pic18f2220/2320/4220/4320 the ccpr1h register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm opera- tion. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or two bits of the tmr2 prescaler, the ccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the following equation. equation 15-3: 15.5.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 register. 2. set the pwm duty cycle by writing to the ccpr1l register and the ccp1con<5:4> bits. 3. make the ccp1 pin an output by clearing the trisc<2> bit. 4. set the tmr2 prescale value and enable timer2 by writing to t2con. 5. configure the ccp1 module for pwm operation. table 15-4: example pwm frequencies and resolutions at 40 mhz table 15-5: registers associated with pwm and timer2 note: if the pwm duty cycle value is longer than the pwm period, the ccp1 pin will not be cleared. pwm resolution (max) = f osc f pwm log log(2) bits ? ? ? ? pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu ccp2con ? ? dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 --00 0000 --00 0000 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 qq00 0000 qq00 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by pwm and timer2. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 140 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 141 pic18f2220/2320/4220/4320 16.0 enhanced capture/ compare/pwm (eccp) module in 40 and 44-pin devices, the ccp1 module is implemented as a standard ccp module with enhanced pwm capabilities. operation of the capture, compare and standard single output pwm modes is described in section 15.0 ?capture/compare/pwm (ccp) modules? . discussion in that section relating to pwm frequency and duty cycle also apply to the enhanced pwm mode. the eccp module differs from the ccp with the addi- tion of an enhanced pwm mode which allows for 2 or 4 output channels, user-selectable polarity, dead band control and automatic shutdown and restart. these features are discussed in detail in section 16.4 ?enhanced pwm mode? . the control register for ccp1 is shown in register 16-1. it differs from the ccp1con register of pic18f2x20 devices in that the two most significant bits are implemented to control enhanced pwm functionality. register 16-1: ccp1con register for enhanced ccp operation (pic18f4x20 only) note: the eccp (enhanced capture/ compare/ pwm) module is only available on pic18f4x20 devices. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 bit 7-6 p1m1:p1m0: pwm output configuration bits if ccp1m<3:2> = 00, 01, 10 (capture, compare, or disabled): xx = p1a assigned as capture/compare input; p1b, p1c, p1d assigned as port pins if ccp1m<3:2> = 11 (pwm modes): 00 = single output; p1a modulated; p1b, p1c, p1d assigned as port pins 01 = full-bridge output forward; p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output; p1a, p1b modulated with dead band control; p1c, p1d assigned as port pins 11 = full-bridge output reverse; p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dc1b1:dc1b0: pwm duty cycle least significant bits capture mode: unused. compare mode: unused. pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m3:ccp1m0: eccp1 mode select bits 0000 = capture/compare/pwm off (resets eccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (eccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (eccp1if bit is set) 1001 = compare mode, clear output on match (eccp1if bit is set) 1010 = compare mode, generate software interrupt on match (eccp1if bit is set, eccp1 pin operates as a port pin for input and output) 1011 = compare mode, trigger special event (eccp1if bit is set, eccp resets tmr1or tmr2 and starts an a/d conversion if the a/d module is enabled) 1100 = pwm mode, p1a, p1c active-high, p1b, p1d active-high 1101 = pwm mode, p1a, p1c active-high, p1b, p1d active-low 1110 = pwm mode, p1a, p1c active-low, p1b, p1d active-high 1111 = pwm mode, p1a, p1c active-low, p1b, p1d active-low legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 142 ? 2003 microchip technology inc. in addition to the expanded functions of the ccp1con register, the eccp module has two additional registers associated with enhanced pwm operation and auto-shutdown features: pwm1con eccpas all other registers associated with the eccp module are identical to those used for the ccp1 module in pic18f2x20 devices, including register and individual bit names. likewise, the timer assignments and inter- actions between the two ccp modules are identical, regardless of whether ccp1 is a standard or enhanced module. 16.1 eccp outputs the enhanced ccp module may have up to four outputs depending on the selected operating mode. these out- puts, designated p1a through p1d, are multiplexed with i/o pins on portc and portd. the pin assignments are summarized in table 16-1. to configure i/o pins as pwm outputs, the proper pwm mode must be selected by setting the p1mn and ccp1mn bits (ccp1con<7:6> and <3:0>, respec- tively). the appropriate trisc and trisd direction bits for the port pins must also be set as outputs. 16.2 capture and compare modes the capture and compare modes of the eccp module are identical in operation to that of ccp1, as discussed in section 15.3 ?capture mode? and section 15.4 ?compare mode? . no changes are required when moving between these modules on pic18f2x20 and pic18f4x20 devices. 16.3 standard pwm mode when configured in single output mode, the eccp module functions identically to the standard ccp module in pwm mode, as described in section 15.4 ?compare mode? . table 16-1: pin assignments for various eccp modes note: when setting up single output pwm opera- tions, users are free to use either of the pro- cesses described in section 15.5.3 ?setup for pwm operation? or section 16.4.7 ?setup for pwm operation? . the latter is more generic but will work for either single or multi output pwm. eccp mode ccp1con configuration rc2 rd5 rd6 rd7 compatible ccp 00xx11xx ccp1 rd5/psp5 rd6/psp6 rd7/psp7 dual pwm 10xx11xx p1a p1b rd6/psp6 rd6/psp6 quad pwm x1xx11xx p1a p1b p1c p1d legend: x = don?t care. shaded cells indicate pin assignments not used by eccp in a given mode. note 1: tris register values must be configured appropriately. 2: with eccp in dual or quad pwm mode, the psp input/output control of portd is overridden by p1b, p1c and p1d.
? 2003 microchip technology inc. ds39599c-page 143 pic18f2220/2320/4220/4320 16.4 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is an upwardly compatible version of the standard ccp module and offers up to four outputs, designated p1a through p1d. users are also able to select the polarity of the signal (either active-high or active-low). the module?s output mode and polarity are configured by setting the p1m1:p1m0 and ccp1m3:ccp1m0 bits of the ccp1con register (ccp1con<7:6> and ccp1con<3:0>, respectively). figure 16-1 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when timer2 resets) in order to pre- vent glitches on any of the outputs. the exception is the pwm delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffering, the module waits until the assigned timer resets instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate trisd bits for output. 16.4.1 pwm output configurations the p1m1:p1m0 bits in the ccp1con register allow one of four configurations: single output half-bridge output full-bridge output, forward mode full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 15.5 ?pwm mode? . the half- bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 16-2. figure 16-1: simplified block diagram of the enhanced pwm module ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers ccp1con<5:4> clear timer, set ccp1 pin and latch d.c. note: the 8-bit timer tmr2 register is concatenated with the 2-bit internal q clock or 2 bits of the prescaler to create the 10-bit t ime base. trisd<4> rc2/ccp1/p1a trisd<5> rd5/psp5/p1b trisd<6> rd6/psp6/p1c trisd<7> rd7/psp7/p1d output controller p1m1<1:0> 2 ccp1m<3:0> 4 pwm1con ccp1/p1a p1b p1c p1d
pic18f2220/2320/4220/4320 ds39599c-page 144 ? 2003 microchip technology inc. figure 16-2: pwm output relationships (active-high state) figure 16-3: pwm output relationships (active-low state) relationships: period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) delay = 4 * t osc * (pwm1con<6:0>) note 1: dead band delay is programmed using the pwm1con register (see section 16.4.4 ?programmable dead band delay? ). 0 period 00 10 01 11 signal pr2+1 ccp1con <7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) 0 period 00 10 01 11 signal pr2+1 ccp1con <7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1)
? 2003 microchip technology inc. ds39599c-page 145 pic18f2220/2320/4220/4320 16.4.2 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the pwm output sig- nal is output on the rc2/ccp1/p1a pin, while the com- plementary pwm output signal is output on the rd5/ psp5/p1b pin (figure 16-4). this mode can be used for half-bridge applications, as shown in figure 16-5, or for full-bridge applications where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead band delay can be used to prevent shoot-through current in half-bridge power devices. the value of bits pdc6:pdc0 sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 16.4.4 ?programmable dead band delay? for more details of the dead band delay operations. since the p1a and p1b outputs are multiplexed with the portc<2> and portd<5> data latches, the trisc<2> and trisd<5> bits must be cleared to configure p1a and p1b as outputs. figure 16-4: half-bridge pwm output figure 16-5: examples of half-bri dge output mode applications period duty cycle td td (1) p1a (2) p1b (2) td = dead band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. pic18f4220/4320 p1a p1b fet driver fet driver v+ v- load + v - + v - fet driver fet driver v+ v- load fet driver fet driver pic18f4220/4320 p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit
pic18f2220/2320/4220/4320 ds39599c-page 146 ? 2003 microchip technology inc. 16.4.3 full-bridge mode in full-bridge output mode, four pins are used as out- puts; however, only two outputs are active at a time. in the forward mode, pin rc2/ccp1/p1a is continuously active and pin rd7/psp7/p1d is modulated. in the reverse mode, rd6/psp6/p1c pin is continuously active and rd5/psp5/p1b pin is modulated. these are illustrated in figure 16-6. p1a, p1b, p1c and p1d outputs are multiplexed with the portc<2> and portd<5:7> data latches. the trisc<2> and trisd<5:7> bits must be cleared to make the p1a, p1b, p1c and p1d pins output. figure 16-6: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. note 2: output signal is shown as active-high.
? 2003 microchip technology inc. ds39599c-page 147 pic18f2220/2320/4220/4320 figure 16-7: example of full-bridge application 16.4.3.1 direction change in full-bridge mode in the full-bridge output mode, the p1m1 bit in the ccp1con register allows users to control the forward/ reverse direction. when the application firmware changes this direction control bit, the module will assume the new direction on the next pwm cycle. just before the end of the current pwm period, the mod- ulated outputs (p1b and p1d) are placed in their inactive state, while the unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. this occurs in a time interval of 4 t osc * (timer2 prescale value) before the next pwm period begins. the timer2 prescaler will be either 1, 4 or 16, depending on the value of the t2ckps bit (t2con<1:0>). during the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (p1b and p1d) remain inactive. this relationship is shown in figure 16-8. note that in the full-bridge output mode, the eccp module does not provide any dead band delay. in gen- eral, since only one output is modulated at all times, dead band delay is not required. however, there is a situation where a dead band delay might be required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. figure 16-9 shows an example where the pwm direc- tion changes from forward to reverse at a near 100% duty cycle. at time t1, the outputs p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices qc and qd (see figure 16-7) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. reduce pwm for a pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. pic18f4220/4320 p1a p1c fet driver fet driver v+ v- load fet driver fet driver p1b p1d qa qb qd qc
pic18f2220/2320/4220/4320 ds39599c-page 148 ? 2003 microchip technology inc. figure 16-8: pwm direction change figure 16-9: pwm direction chang e at near 100% duty cycle (1) dc period (1) signal note 1: the direction bit in the ccp1 control register (ccp 1con<7>) is written any time during the pwm cycle. 2: when changing directions, the p1a and p1c signals switch before the end of the current pwm cycle at intervals of 4 t osc , 16 t osc or 64 t osc , depending on the timer2 prescaler value. the modulated p1b and p1d signals are inactive at this time. period (note 2) p1a (active high) p1b (active high) p1c (active high) p1d (active high) dc forward period reverse period p1a t on (2) t off (3) t = t off ? t on (2,3) p1b p1c p1d external switch d potential shoot-through current note 1: all signals are shown as active-high. 2: t on is the turn-on delay of power switch qc and its driver. 3: t off is the turn-off delay of power switch qd and its driver. external switch c t1 dc dc
? 2003 microchip technology inc. ds39599c-page 149 pic18f2220/2320/4220/4320 16.4.4 programmable dead band delay in half-bridge applications, where all power switches are modulated at the pwm frequency at all times, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot- through current ) may flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flow- ing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally program- mable dead band delay is available to avoid shoot- through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 16-4 for illustration. the lower seven bits of the pwm1con register (register 16-2) set the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). 16.4.5 enhanced pwm auto-shutdown when the eccp is programmed for any of the enhanced pwm modes, the active output pins may be configured for auto-shutdown. auto-shutdown immedi- ately places the enhanced pwm output pins into a defined shutdown state when a shutdown event occurs. a shutdown event can be caused by either of the two comparator modules or the int0 pin (or any combina- tion of these three sources). the comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. if the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. alternatively, a digital signal on the int0 pin can also trigger a shutdown. the auto- shutdown feature can be disabled by not selecting any auto-shutdown sources. the auto-shutdown sources to be used are selected using the eccpas2:eccpas0 bits (eccpas<6:4>). when a shutdown occurs, the output pins are asyn- chronously placed in their shutdown states, specified by the pssac1:pssac0 and pssbd1:pssbd0 bits (eccpas<3:0>). each pin pair (p1a/p1c and p1b/ p1d) may be set to drive high, drive low or be tri-stated (not driving). the eccpase bit (eccpas<7>) is also set to hold the enhanced pwm outputs in their shutdown states. the eccpase bit is set by hardware when a shutdown event occurs. if automatic restarts are not enabled, the eccpase bit is cleared by firmware when the cause of the shutdown clears. if automatic restarts are enabled, the eccpase bit is automatically cleared when the cause of the auto-shutdown has cleared. if the eccpase bit is set when a pwm period begins, the pwm outputs remain in their shutdown state for that entire pwm period. when the eccpase bit is cleared, the pwm outputs will return to normal operation at the beginning of the next pwm period. register 16-2: pwm1con: pwm configurat ion register note: writing to the eccpase bit is disabled while a shutdown condition is active. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 bit 7 bit 0 bit 7 prsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpase must be cleared in software to restart the pwm bit 6-0 pdc<6:0>: pwm delay count bits number of f osc /4 (4 * t osc ) cycles between the scheduled time when a pwm signal should transition active and the actual time it transitions active. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 150 ? 2003 microchip technology inc. register 16-3: eccpas: enhanced capture/compare/pwm auto-shutdown control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 bit 7 bit 0 bit 7 eccpase: eccp auto-shutdown event status bit 0 = eccp outputs are operating 1 = a shutdown event has occurred; eccp outputs are in shutdown state bit 6-4 eccpas<2:0>: eccp auto-shutdown source select bits 000 = auto-shutdown is disabled 001 = comparator 1 output 010 = comparator 2 output 011 = either comparator 1 or 2 100 = int0 101 = int0 or comparator 1 110 = int0 or comparator 2 111 = int0 or comparator 1 or comparator 2 bit 3-2 pssac<1:0>: pin a and c shutdown state control bits 00 = drive pins a and c to ? 0 ? 01 = drive pins a and c to ? 1 ? 1x = pins a and c tri-state bit 1-0 pssbd<1:0>: pin b and d shutdown state control bits 00 = drive pins b and d to ? 0 ? 01 = drive pins b and d to ? 1 ? 1x = pins b and d tri-state legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 151 pic18f2220/2320/4220/4320 16.4.5.1 auto-shutdown and automatic restart the auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. this is enabled by setting the prsen bit of the pwm1con register (pwm1con<7>). in shutdown mode with prsen = 1 (figure 16-10), the eccpase bit will remain set for as long as the cause of the shutdown continues. when the shutdown condi- tion clears, the eccpase bit is cleared. if prsen = 0 (figure 16-11), once a shutdown condition occurs, the eccpase bit will remain set until it is cleared by firm- ware. once eccpase is cleared, the enhanced pwm will resume at the beginning of the next pwm period. independent of the prsen bit setting, if the auto- shutdown source is one of the comparators, the shut- down condition is a level. the eccpase bit cannot be cleared as long as the cause of the shutdown persists. the auto-shutdown mode can be forced by writing a ? 1 ? to the eccpase bit. 16.4.6 start-up considerations when the eccp module is used in the pwm mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the pwm output pins. when the microcontroller is released from reset, all of the i/o pins are in the high-impedance state. the exter- nal circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels or activates the pwm output(s). the ccp1m1:ccp1m0 bits (ccp1con<1:0>) allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polar- ities must be selected before the pwm pins are config- ured as outputs. changing the polarity configuration while the pwm pins are configured as outputs is not recommended since it may result in damage to the application circuits. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the eccp module may cause damage to the application circuit. the eccp module must be enabled in the proper output mode and complete a full pwm cycle before con- figuring the pwm pins as outputs. the completion of a full pwm cycle is indicated by the tmr2if bit being set as the second pwm period begins. figure 16-10: pwm auto-shutdown (prsen = 1 , auto-restart enabled) figure 16-11: pwm auto-shutdown (prsen = 0 , auto-restart disabled) note: writing to the eccpase bit is disabled while a shutdown condition is active. shutdown pwm eccpase bit activity event pwm period pwm period pwm period duty cycle dead time duty cycle dead time duty cycle dead time shutdown pwm eccpase bit activity event pwm period pwm period pwm period eccpase cleared by firmware duty cycle dead time duty cycle dead time duty cycle dead time
pic18f2220/2320/4220/4320 ds39599c-page 152 ? 2003 microchip technology inc. 16.4.7 setup for pwm operation the following steps should be taken when configuring the eccp1 module for pwm operation: 1. configure the pwm pins p1a and p1b (and p1c and p1d, if used) as inputs by setting the corresponding trisc and trisd bits. 2. set the pwm period by loading the pr2 register. 3. configure the eccp module for the desired pwm mode and configuration by loading the ccp1con register with the appropriate values: select one of the available output configurations and direction with the p1m1:p1m0 bits. select the polarities of the pwm output signals with the ccp1m3:ccp1m0 bits. 4. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 5. for half-bridge output mode, set the dead band delay by loading pwm1con<6:0> with the appropriate value. 6. if auto-shutdown operation is required, load the eccpas register: select the auto-shutdown sources using the eccpas<2:0> bits. select the shutdown states of the pwm output pins using pssac1:pssac0 and pssbd1:pssbd0 bits. set the eccpase bit (eccpas<7>). configure the comparators using the cmcon register. configure the comparator inputs as analog inputs. 7. if auto-restart operation is required, set the prsen bit (pwm1con<7>). 8. configure and start tmr2: clear the tmr2 interrupt flag bit by clearing the tmr2if bit (pir1<1>). set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). enable timer2 by setting the tmr2on bit (t2con<2>). 9. enable pwm outputs after a new pwm cycle has started: wait until tmr2 overflows (tmr2if bit is set). enable the ccp1/p1a, p1b, p1c and/or p1d pin outputs by clearing the respective trisc and trisd bits. clear the eccpase bit (eccpas<7>). 16.4.8 operation in power managed modes in sleep mode, all clock sources are disabled. timer2 will not increment and the state of the module will not change. if the eccp pin is driving a value, it will con- tinue to drive that value. when the device wakes up, it will continue from this state. if two-speed start-ups are enabled, the initial start-up frequency from intosc and the postscaler may not be stable immediately. in pri_idle mode, the primary clock will continue to clock the eccp module without change. in all other power managed modes, the selected power managed mode clock will clock timer2. other power managed mode clocks will most likely be different than the primary clock frequency. 16.4.8.1 operation with fail-safe clock monitor if the fail-safe clock monitor is enabled (config1h<6> is programmed), a clock failure will force the device into the rc_run power managed mode and the oscfif bit (pir2<7>) will be set. the eccp will then be clocked from the internal oscillator clock source which may have a different clock frequency than the primary clock. by loading the ircf2:ircf0 bits on resets, the user can obtain a frequency higher than the default intrc clock source in the event of a clock failure. see the previous section for additional details. 16.4.9 effects of a reset both power-on and subsequent resets will force all ports to input mode and the ccp registers to their reset states. this forces the enhanced ccp module to reset to a state compatible with the standard ccp module.
? 2003 microchip technology inc. ds39599c-page 153 pic18f2220/2320/4220/4320 table 16-2: registers associated with enhanced pwm and timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u rcon ipen ? ? ri to pd por bor 0--1 11qq 0--q qquu pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 tmr2 timer2 module register 0000 0000 0000 0000 pr2 timer2 module period register 1111 1111 1111 1111 t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 trisc portc data direction register 1111 1111 1111 1111 trisd portd data direction register 1111 1111 1111 1111 ccpr1h enhanced capture/compare/pwm register 1 high byte xxxx xxxx uuuu uuuu ccpr1l enhanced capture/compare/pwm register 1 low byte xxxx xxxx uuuu uuuu ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 eccpas eccpase eccpas2 eccpas1 eccpas0 pssac1 pssac0 pssbd1 pssbd0 0000 0000 0000 0000 pwm1con prsen pdc6 pdc5 pdc4 pdc3 pdc2 pdc1 pdc0 0000 0000 0000 0000 osccon idlen ircf2 ircf1 ircf0 osts iofs scs1 scs0 0000 q000 0000 q000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the eccp module in enhanced pwm mode.
pic18f2220/2320/4220/4320 ds39599c-page 154 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 155 pic18f2220/2320/4220/4320 17.0 master synchronous serial port (mssp) module 17.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the mssp module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: master mode multi-master mode slave mode 17.2 control registers the mssp module has three associated registers. these include a status register (sspstat) and two control registers (sspcon1 and sspcon2). the use of these registers and their individual configuration bits differ significantly, depending on whether the mssp module is operated in spi or i 2 c mode. additional details are provided under the individual sections. 17.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: serial data out (sdo) ? rc5/sdo serial data in (sdi) ? rc4/sdi/sda serial clock (sck) ? rc3/sck/scl additionally, a fourth pin may be used when in a slave mode of operation: slave select (ss ) ? ra5/an4/ss /lvdin/c2out register 17-1 shows the block diagram of the mssp module when operating in spi mode. figure 17-1: mssp block diagram (spi mode) ( ) read write internal data bus sspsr reg sspm3:sspm0 bit 0 shift clock ss control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to tx/rx in sspsr tris bit 2 smp:cke rc5/sdo sspbuf reg ra5/an4/ss / rc3/sck/ scl rc4/sdi/sda lvdin/c2out
pic18f2220/2320/4220/4320 ds39599c-page 156 ? 2003 microchip technology inc. 17.3.1 registers the mssp module has four registers for spi mode operation. these are: mssp control register 1 (sspcon1) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) ? not directly accessible sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 regis- ter is readable and writable. the lower six bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. register 17-1: sspstat: mssp status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock edge select bit when ckp = 0 : 1 = data transmitted on rising edge of sck 0 = data transmitted on falling edge of sck when ckp = 1 : 1 = data transmitted on falling edge of sck 0 = data transmitted on rising edge of sck bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write bit information used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only. bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 157 pic18f2220/2320/4220/4320 register 17-2: sspcon1: mssp control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit spi slave mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode.the user must read the sspbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow note: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. bit 5 sspen: synchronous serial port enable bit 1 = enables serial port and configures sck, sdo, sdi and ss as serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when the mssp is enabled in spi mode, these pins must be properly configured as input or output. bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note: bit combinations not specifically listed here are either reserved or implemented in i 2 c mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 158 ? 2003 microchip technology inc. 17.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) the mssp consists of a transmit/receive shift regis- ter (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspbuf register. then the buffer full detect bit, bf (sspstat<0>), and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspbuf register completed successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. buffer full bit, bf (sspstat<0>), indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has com- pleted. the sspbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 17-1 shows the loading of the sspbuf (sspsr) for data transmission. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the mssp status register (sspstat) indicates the various status conditions. example 17-1: loading the sspbuf (sspsr) register loop btfss sspstat, bf ;has data been received(transmit complete)? bra loop ;no movf sspbuf, w ;wreg reg = contents of sspbuf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf sspbuf ;new data to xmit
? 00xxb serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm3:sspm0 = 010xb serial clock
pic18f2220/2320/4220/4320 ds39599c-page 160 ? 2003 microchip technology inc. 17.3.5 master mode the master can initiate the data transfer at any time because it controls the sck. the master determines when the slave (processor 2, figure 17-2) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be dis- abled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately program- ming the ckp bit (sspcon1<4>). this then, would give waveforms for spi communication as shown in figure 17-3, figure 17-5 and figure 17-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 t cy ) f osc /64 (or 16 t cy ) (timer2 output)/2 the maximum data rate is approximately 3.0 mbps, limited by timing requirements (see table 26-14 through table 26-17). figure 17-3 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 17-3: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2
? 2003 microchip technology inc. ds39599c-page 161 pic18f2220/2320/4220/4320 17.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in power managed modes, the slave can trans- mit/receive data. when a byte is received, the device will wake-up from power managed modes. 17.3.7 slave select control the ss pin allows a master controller to select one of several slave controllers for communications in sys- tems with more than one slave. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 04h). the ss pin is configured for input by setting trisa<5>. when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is tri-stated, even if in the middle of a transmitted byte. external pull-up/pull-down resistors may be desirable, depending on the application. when the spi module resets, sspsr is cleared. this can be done by either driving the ss pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdo pin can be connected to the sdi pin. when the spi needs to operate as a receiver the sdo pin can be configured as an input. this disables transmissions from the sdo. the sdi can always be left as an input (sdi function) since it cannot create a bus conflict. figure 17-4: slave synchronization waveform note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset when the ss pin is set high. 2: if the spi is used in slave mode with cke set, then the ss pin control must be enabled. sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 next q4 cycle after q2
pic18f2220/2320/4220/4320 ds39599c-page 162 ? 2003 microchip technology inc. figure 17-5: spi mode waveform (slave mode with cke = 0 ) figure 17-6: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag optional next q4 cycle after q2 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspbuf sspsr to sspbuf ss flag not optional next q4 cycle after q2
? 2003 microchip technology inc. ds39599c-page 163 pic18f2220/2320/4220/4320 17.3.8 master in power managed modes in master mode, module clocks may be operating at a different speed than when in full power mode, or in the case of the sleep power managed mode, all clocks are halted. in most power managed modes, a clock is provided to the peripherals and is derived from the primary clock source, the secondary clock (timer1 oscillator at 32.768 khz) or the internal oscillator block (one of eight frequen- cies between 31 khz and 8 mhz). see section 2.7 ?clock sources and oscillator switching? for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the con- troller from a power managed mode when the master completes sending data. if an exit from a power managed mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will pause until the device wakes from the power managed mode. after the device returns to full power mode, the module will resume transmitting and receiving data. 17.3.8.1 slave in power managed modes in slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power managed mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if mssp interrupts are enabled, will wake the device from a power managed mode. 17.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 17.3.10 bus mode compatibility table 17-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 17-1: spi bus modes there is also an smp bit which controls when the data is sampled. table 17-2: registers associated with spi operation standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 trisc portc data direction register 1111 1111 1111 1111 sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 0000 0000 trisa trisa7 (1) trisa6 (1) porta data direction register --11 1111 --11 1111 sspstat smp cke d/a p s r/w ua bf 0000 0000 0000 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp in spi mode. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 164 ? 2003 microchip technology inc. 17.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master func- tion). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: serial clock (scl) ? rc3/sck/scl serial data (sda) ? rc4/sdi/sda the user must configure these pins as inputs using the trisc<4:3> bits. figure 17-7: mssp block diagram (i 2 c mode) 17.4.1 registers the mssp module has six registers for i 2 c operation. these are: mssp control register 1 (sspcon1) mssp control register 2 (sspcon2) mssp status register (sspstat) serial receive/transmit buffer (sspbuf) mssp shift register (sspsr) ? not directly accessible mssp address register (sspadd) sspcon1, sspcon2 and sspstat are the control and status registers in i 2 c mode operation. the sspcon1 and sspcon2 registers are readable and writable. the lower six bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. sspsr is the shift register used for shifting data in or out. sspbuf is the buffer register to which data bytes are written to or read from. sspadd register holds the slave device address when the ssp is configured in i 2 c slave mode. when the ssp is configured in master mode, the lower seven bits of sspadd act as the baud rate generator reload value. in receive operations, sspsr and sspbuf together create a double-buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not double- buffered. a write to sspbuf will write to both sspbuf and sspsr. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg ) rc3/sck/ shift clock msb lsb rc4/sdi/ sda scl
? 2003 microchip technology inc. ds39599c-page 165 pic18f2220/2320/4220/4320 register 17-3: sspstat: mssp status register (i 2 c mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled 0 = slew rate control enabled bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last note: this bit is cleared on reset when sspen is cleared or a start bit has been detected. bit 3 s: start bit 1 = indicates that a start bit has been detected last 0 = start bit was not detected last note: this bit is cleared on reset when sspen is cleared or a stop bit has been detected. bit 2 r/w : read/write bit information (i 2 c mode only) in slave mode: 1 = read 0 = write note: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. in master mode: 1 = transmit is in progress 0 = transmit is not in progress note: or?ing this bit with the sspcon2 bi ts, sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty in receive mode: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 166 ? 2003 microchip technology inc. register 17-4: sspcon1: mssp control register 1 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: synchronous serial port enable bit 1 = enables the serial port and configures the sda and scl pins as the serial port pins 0 = disables serial port and configures these pins as i/o port pins note: when enabled, the sda and scl pins must be configured as input pins. bit 4 ckp: sck release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1011 = i 2 c firmware controlled master mode (slave idle) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address note: bit combinations not specifically listed here are either reserved, or implemented in spi mode only. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 167 pic18f2220/2320/4220/4320 register 17-5: sspcon2: mssp control register 2 (i 2 c mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) 1 = not acknowledge 0 = acknowledge note: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. bit 4 acken: acknowledge sequence enable bit (master receive mode only) 1 = initiate acknowledge sequence on sda and scl pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (master mode only) 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled/stretch enabled bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 168 ? 2003 microchip technology inc. 17.4.2 operation the mssp module functions are enabled by setting mssp enable bit, sspen (sspcon1<5>). the sspcon1 register allows control of the i 2 c oper- ation. four mode selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) i 2 c slave mode (7-bit address) i 2 c slave mode (10-bit address) i 2 c slave mode (7-bit address), with start and stop bit interrupts enabled i 2 c slave mode (10-bit address), with start and stop bit interrupts enabled i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the scl and sda pins to be open-drain, pro- vided these pins are programmed to inputs by setting the appropriate trisc bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the scl and sda pins. 17.4.3 slave mode in slave mode, the scl and sda pins must be config- ured as inputs (trisc<4:3> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an address match. through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware automati- cally will generate the acknowledge (ack ) pulse and load the sspbuf register with the received value currently in the sspsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: the buffer full bit, bf (sspstat<0>), was set before the transfer was received. the overflow bit, sspov (sspcon1<6>), was set before the transfer was received. in this case, the sspsr register value is not loaded into the sspbuf but bit sspif (pir1<3>) is set. the bf bit is cleared by reading the sspbuf register, while bit sspov is cleared by software. the scl clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter #100 and parameter #101. 17.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspsr register. all incom- ing bits are sampled with the rising edge of the clock (scl) line. the value of register sspsr<7:1> is com- pared to the value of the sspadd register. the address is compared on the falling edge of the eighth clock (scl) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspsr register value is loaded into the sspbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. mssp interrupt flag bit, sspif (pir1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth scl pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspif, bf and bit ua (sspstat<1>) are set). 2. update the sspadd register with second (low) byte of address (clears bit ua and releases the scl line). 3. read the sspbuf register (clears bit bf) and clear flag bit sspif. 4. receive second (low) byte of address (bits sspif, bf and ua are set). 5. update the sspadd register with the first (high) byte of address. if match releases scl line, this will clear bit ua. 6. read the sspbuf register (clears bit bf) and clear flag bit sspif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspif and bf are set). 9. read the sspbuf register (clears bit bf) and clear flag bit sspif.
? 2003 microchip technology inc. ds39599c-page 169 pic18f2220/2320/4220/4320 17.4.3.2 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and the sda line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit, bf (sspstat<0>), is set or bit, sspov (sspcon1<6>), is set. an mssp interrupt is generated for each data transfer byte. flag bit, sspif (pir1<3>), must be cleared in software. the sspstat register is used to determine the status of the byte. if sen is enabled (sspcon2<0> = 1 ), rc3/sck/scl will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspcon1<4>). see section 17.4.4 ?clock stretching? for more detail. 17.4.3.3 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register. the ack pulse will be sent on the ninth bit and pin rc3/sck/scl is held low regardless of sen (see section 17.4.4 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then pin rc3/ sck/scl should be enabled by setting bit, ckp (sspcon1<4>). the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time (figure 17-9). the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. if the sda line is high (not ack ), then the data transfer is com- plete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspstat regis- ter) and the slave monitors for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, pin rc3/sck/scl must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared in software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse.
pic18f2220/2320/4220/4320 ds39599c-page 170 ? 2003 microchip technology inc. figure 17-8: i 2 c slave mode timing with sen = 0 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 2 34 56 7 8 91 234 5 67 89 1 23 45 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp (ckp does not reset to ? 0 ? when sen = 0 )
? 2003 microchip technology inc. ds39599c-page 171 pic18f2220/2320/4220/4320 figure 17-9: i 2 c slave mode timing (transmission, 7-bit address) sda scl sspif (pir1<3>) bf (sspstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software scl held low while cpu responds to sspif from sspif isr data in sampled s ack transmitting data r/w = 1 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspbuf is written in software cleared in software from sspif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software
pic18f2220/2320/4220/4320 ds39599c-page 172 ? 2003 microchip technology inc. figure 17-10: i 2 c slave mode timing with sen = 0 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2 a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) sspov is set because sspbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspadd has taken place
? 2003 microchip technology inc. ds39599c-page 173 pic18f2220/2320/4220/4320 figure 17-11: i 2 c slave mode timing (transmission, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 1 23456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 (pir1<3>) receive second byte of address cleared by hardware when sspadd is updated with low byte of address ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address. sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspbuf to clear bf flag sr cleared in software write of sspbuf initiates transmit cleared in software completion of clears bf flag ckp (sspcon1<4>) ckp is set in software ckp is automatically cleared in hardware holding scl low clock is held low until update of sspadd has taken place data transmission clock is held low until ckp is set to ? 1 ? bf flag is clear third address sequence at the end of the
pic18f2220/2320/4220/4320 ds39599c-page 174 ? 2003 microchip technology inc. 17.4.4 clock stretching both 7 and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the scl pin to be held low at the end of each data receive sequence. 17.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence if the bf bit is set, the ckp bit in the sspcon1 register is automat- ically cleared, forcing the scl output to be held low. the ckp being cleared to ? 0 ? will assert the scl line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the scl line low, the user has time to service the isr and read the contents of the sspbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 17-13). 17.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode, during the address sequence, clock stretching automatically takes place but the ckp bit is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 17.4.4.3 clock stretching for 7-bit slave transmit mode 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmis- sion is allowed to continue. by holding the scl line low, the user has time to service the isr and load the contents of the sspbuf before the master device can initiate another transmit sequence (see figure 17-9). 17.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is con- trolled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 17-11). note 1: if the user reads the contents of the sspbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit.
? 2003 microchip technology inc. ds39599c-page 175 pic18f2220/2320/4220/4320 17.4.4.5 clock synchronization and the ckp bit (sen = 1 ) the sen bit is also used to synchronize writes to the ckp bit. if a user clears the ckp bit, the scl output is forced to ? 0 ?. when the sen bit is set to ? 1 ?, setting the ckp bit will not assert the scl output low until the scl output is already sampled low. if the user attempts to drive scl low, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 17-12). figure 17-12: clock synchronization timing note: if the sen bit is ? 0 ?, clearing the ckp bit will result in immediately driving the scl output to ? 0 ? regardless of the current state. sda scl dx-1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device deasserts clock master device asserts clock
pic18f2220/2320/4220/4320 ds39599c-page 176 ? 2003 microchip technology inc. figure 17-13: i 2 c slave mode timing with sen = 1 (reception, 7-bit address) sda scl sspif bf (sspstat<0>) sspov (sspcon1<6>) s 1 234 56789 1 2345 6789 1 2345 789 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspbuf is read bus master terminates transfer sspov is set because sspbuf is still full. ack is not sent. d2 6 (pir1<3>) ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs
? 2003 microchip technology inc. ds39599c-page 177 pic18f2220/2320/4220/4320 figure 17-14: i 2 c slave mode timing with sen = 1 (reception, 10-bit address) sda scl sspif bf (sspstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2 a1a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 (pir1<3>) cleared in software receive second byte of address cleared by hardware when sspadd is updated with low byte of address after falling edge ua (sspstat<1>) clock is held low until update of sspadd has taken place ua is set indicating that the sspadd needs to be updated ua is set indicating that sspadd needs to be updated cleared by hardware when sspadd is updated with high byte of address after falling edge sspbuf is written with contents of sspsr dummy read of sspbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspcon1<6>) ckp written to ? 1 ? note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspadd has taken place of ninth clock. of ninth clock sspov is set because sspbuf is still full. ack is not sent. dummy read of sspbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1
pic18f2220/2320/4220/4320 ds39599c-page 178 ? 2003 microchip technology inc. 17.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable bit (gcen) is enabled (sspcon2<7> set). following a start bit detect, 8 bits are shifted into the sspsr and the address is com- pared against the sspadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspsr is transferred to the sspbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspif interrupt flag bit is set. when the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the sspbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit mode, the sspadd is required to be updated for the second half of the address to match and the ua bit is set (sspstat<1>). if the general call address is sampled when the gcen bit is set while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 17-15). figure 17-15: slave mode general call address sequence (7 or 10-bit address mode) sda scl s sspif bf (sspstat<0>) sspov (sspcon1<6>) cleared in software sspbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack, set interrupt ? 0 ? ? 1 ?
? 2003 microchip technology inc. ds39599c-page 179 pic18f2220/2320/4220/4320 17.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspcon1 and by setting the sspen bit. in master mode, the scl and sda lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sda and scl. 2. assert a repeated start condition on sda and scl. 3. write to the sspbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sda and scl. the following events will cause ssp interrupt flag bit, sspif, to be set (ssp interrupt if enabled): start condition stop condition data transfer byte transmitted/received acknowledge transmit repeated start figure 17-16: mssp block diagram (i 2 c master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condi- tion is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. read write sspsr start bit, stop bit, sspbuf internal data bus set/reset, s, p, wcol (sspstat) shift clock msb lsb sda acknowledge generate scl scl in bus collision sda in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspadd<6:0> baud set sspif, bclif reset ackstat, pen (sspcon2) rate generator sspm3:sspm0 start bit detect stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv
pic18f2220/2320/4220/4320 ds39599c-page 180 ? 2003 microchip technology inc. 17.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted con- tains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmit- ted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode operation is used to set the scl clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 17.4.7 ?baud rate? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspcon2<0>). 2. sspif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspbuf with the slave address to transmit. 4. address is shifted out the sda pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 7. the user loads the sspbuf with eight bits of data. 8. data is shifted out the sda pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspcon2 register (sspcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspcon2<2>). 12. interrupt is generated once the stop condition is complete.
? 0 ? and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the scl pin will remain in its last state. table 17-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. 17.4.7.1 baud rate generation in power managed modes when the device is operating in a power managed mode, the clock source to the baud rate generator may change frequency or stop, depending on the power managed mode and clock source selected. in most power modes, the baud rate generator continues to be clocked but may be clocked from the primary clock (selected in a configuration word), the secondary clock (timer1 oscillator at 32.768 khz) or the internal oscillator block (one of eight frequencies between 31 khz and 8 mhz). if the sleep mode is selected, all clocks are stopped and the baud rate generator will not be clocked. figure 17-17: baud rate generator block diagram table 17-3: i 2 c clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspadd<6:0> sspm3:sspm0 scl reload control reload f osc f cy f cy *2 sspadd value (see register 17-4, mode 1000) f scl (2) (2 rollovers of brg) 40 mhz 10 mhz 20 mhz 18h 400 khz (1) 40 mhz 10 mhz 20 mhz 1fh 312.5 khz 40 mhz 10 mhz 20 mhz 63h 100 khz 16 mhz 4 mhz 8 mhz 09h 400 khz (1) 16 mhz 4 mhz 8 mhz 0bh 308 khz 16 mhz 4 mhz 8 mhz 27h 100 khz 4 mhz 1 mhz 2 mhz 02h 333 khz (1) 4 mhz 1 mhz 2 mhz 09h 100khz 4 mhz 1 mhz 2 mhz 00h 1 mhz (1) note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. 2: actual clock rate will depend on bus conditions. bus capacitance can increase rise time and extend the low time of the clock period, reducin g the effective clock frequency (see section 17.4.7.2 ?clock arbitration? ).
pic18f2220/2320/4220/4320 ds39599c-page 182 ? 2003 microchip technology inc. 17.4.7.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 17-18). figure 17-18: baud rate generator timing with clock arbitration sda scl scl deasserted but slave holds dx-1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles
? 2003 microchip technology inc. ds39599c-page 183 pic18f2220/2320/4220/4320 17.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start condition enable bit, sen (sspcon2<0>). if the sda and scl pins are sampled high, the baud rate gener- ator is reloaded with the contents of sspadd<6:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit (sspstat<3>) to be set. following this, the baud rate generator is reloaded with the con- tents of sspadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspcon2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. 17.4.8.1 wcol status flag if the user writes the sspbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 17-19: first start bit timing note: if at the beginning of the start condition, the sda and scl pins are already sam- pled low or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
pic18f2220/2320/4220/4320 ds39599c-page 184 ? 2003 microchip technology inc. 17.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sam- pled low, the baud rate generator is loaded with the contents of sspadd<5:0> and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate genera- tor times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded with the contents of sspadd<6:0> and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. following this, the rsen bit (sspcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit (sspstat<3>) will be set. the sspif bit will not be set until the baud rate generator has timed out. immediately following the sspif bit getting set, the user may write the sspbuf with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 17.4.9.1 wcol status flag if the user writes the sspbuf when a repeated start sequence is in progress, the wcol is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 17-20: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low to high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspcon2 is disabled until the repeated start condition is complete. sda scl sr = repeated start write to sspcon2 write to sspbuf occurs here falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit set s (sspstat<3>) t brg t brg sda = 1 , sda = 1 , scl (no change). scl = 1 occurs here. t brg t brg t brg and sets sspif
? 2003 microchip technology inc. ds39599c-page 185 pic18f2220/2320/4220/4320 17.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted (see data hold time specification parameter #106). scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high (see data setup time specification parameter #107). when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit, during the ninth bit time, if an address match occurred or if data was received prop- erly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared; if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged (figure 17-21). after the write to the sspbuf, each bit of address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the fall- ing edge of the eighth clock, the master will deassert the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspcon2<6>). following the falling edge of the ninth clock transmis- sion of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 17.4.10.1 bf status flag in transmit mode, the bf bit (sspstat<0>) is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 17.4.10.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). wcol must be cleared in software. 17.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. 17.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspcon2<3>). the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high to low/ low to high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state, awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspcon2<4>). 17.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 17.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 17.4.11.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic18f2220/2320/4220/4320 ds39599c-page 186 ? 2003 microchip technology inc. figure 17-21: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspbuf is written in software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w , start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 , start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared in software sspbuf written pen cleared in software r/w
? 2003 microchip technology inc. ds39599c-page 187 pic18f2220/2320/4220/4320 figure 17-22: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 1 transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sda = 0 , scl = 1 , while cpu (sspstat<0>) ack last bit is shifted into sspsr and contents are unloaded into sspbuf cleared in software cleared in software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master, set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence, sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence, sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared in software sda = ackdt = 0
pic18f2220/2320/4220/4320 ds39599c-page 188 ? 2003 microchip technology inc. 17.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspcon2<4>). when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 17-23). 17.4.12.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 17.4.13 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspcon2<2>). at the end of a receive/ transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sam- pled low, the baud rate generator is reloaded and counts down to 0. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sam- pled high while scl is high, the p bit (sspstat<4>) is set. a t brg later, the pen bit is cleared and the sspif bit is set (figure 17-24). 17.4.13.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the con- tents of the buffer are unchanged (the write doesn?t occur). figure 17-23: acknowledge sequence waveform figure 17-24: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl set sspif at the end acknowledge sequence starts here, write to sspcon2, acken automatically cleared cleared in t brg t brg of receive ack 8 acken = 1 , ackdt = 0 d0 9 sspif software set sspif at the end of acknowledge sequence cleared in software scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
? 2003 microchip technology inc. ds39599c-page 189 pic18f2220/2320/4220/4320 17.4.14 power managed mode operation while in any power managed mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 17.4.15 effect of a reset a reset disables the mssp module and terminates the current transfer. 17.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspstat<4>) is set or the bus is idle with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be moni- tored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclif bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 17.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif, and reset the i 2 c port to its idle state (figure 17-25). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the con- dition is aborted, the sda and scl lines are deasserted, and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determi- nation of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register or the bus is idle and the s and p bits are cleared. figure 17-25: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt flag (bclif) by the master. by master data changes while scl = 0
pic18f2220/2320/4220/4320 ds39599c-page 190 ? 2003 microchip technology inc. 17.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl is sampled low at the beginning of the start condition (figure 17-26). b) scl is sampled low before sda is asserted low (figure 17-27). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low or the scl pin is already low, then all of the following occur: the start condition is aborted the bclif flag is set the mssp module is reset to its idle state (figure 17-26) the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded from sspadd<6:0> and counts down to 0. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early (figure 17-28). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0 and during this time, if the scl pins are sampled as ? 0 ?, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 17-26: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address fol- lowing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared in software sspif and bclif are cleared in software set bclif, start condition. set bclif.
? 2003 microchip technology inc. ds39599c-page 191 pic18f2220/2320/4220/4320 figure 17-27: bus collision d uring start condition (scl = 0 ) figure 17-28: brg reset due to sda arbitrat ion during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared in software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s set sen, enable start sequence if sda = 1 , scl = 1 less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared in software set sspif sda = 0 , scl = 1 , sda pulled low by other master. reset brg and assert sda. scl pulled low after brg time-out set sspif ? 0 ?
pic18f2220/2320/4220/4320 ds39599c-page 192 ? 2003 microchip technology inc. 17.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indi- cating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sda and the pin is allowed to float high, the brg is loaded with sspadd<6:0> and counts down to 0. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 17-29). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high to low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high to low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 17-30). if at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 17-29: bus collision during a repeat ed start condition (case 1) figure 17-30: bus collision during a repe ated start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared in software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared in software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
? 0 ? (figure 17-31). if the scl pin is sam- pled low before sda is allowed to float high, a bus col- lision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 17-32). figure 17-31: bus collision during a stop condition (case 1) figure 17-32: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
pic18f2220/2320/4220/4320 ds39599c-page 194 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 195 pic18f2220/2320/4220/4320 18.0 addressable universal synchronous asynchronous receiver transmitter (usart) the universal synchronous asynchronous receiver transmitter (usart) module is one of the two serial i/o modules available in the pic18f2x20/4x20 family of microcontrollers. (usart is also known as a serial communications interface or sci.) the usart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the usart can be configured in the following modes: asynchronous (full-duplex) synchronous ? master (half-duplex) synchronous ? slave (half-duplex) the rc6/tx/ck and rc7/rx/dt pins must be config- ured as shown for use with the universal synchronous asynchronous receiver transmitter: spen (rcsta<7>) bit must be set (= 1 ) trisc<7> bit must be set (= 1 ) trisc<6> bit must be cleared (= 0 ) register 18-1 shows the transmit status and control register (txsta) and register 18-2 shows the receive status and control register (rcsta). 18.1 asynchronous operation in power managed modes the usart may operate in asynchronous mode while the peripheral clocks are being provided by the internal oscillator block. this mode makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the osc1 and osc2 pins. the factory calibrates the internal oscillator block out- put (intosc) for 8 mhz. however, this frequency may drift as v dd or temperature changes and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune regis- ter to adjust the intosc output back to 8 mhz. adjust- ing the value in the osctune register allows for fine resolution changes to the system clock source (see section 3.6 ?intosc frequency drift? for more information). the other method adjusts the value in the baud rate generator since there may be not be fine enough res- olution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency.
pic18f2220/2320/4220/4320 ds39599c-page 196 ? 2003 microchip technology inc. register 18-1: txsta: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r-1 r/w-0 csrc tx9 txen sync ?brghtrmttx9d bit 7 bit 0 bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit 1 = transmit enabled 0 = transmit disabled note: sren/cren overrides txen in sync mode. bit 4 sync: usart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 unimplemented: read as ? 0 ? bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2003 microchip technology inc. ds39599c-page 197 pic18f2220/2320/4220/4320 register 18-2: rcsta: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care. synchronous mode ? master: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enable address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 198 ? 2003 microchip technology inc. 18.2 usart baud rate generator (brg) the brg supports both the asynchronous and synchronous modes of the usart. it is a dedicated 8-bit baud rate generator. the spbrg register controls the period of a free-running 8-bit timer. in asynchronous mode, bit brgh (txsta<2>) also con- trols the baud rate. in synchronous mode, bit brgh is ignored. table 18-1 shows the formula for computation of the baud rate for different usart modes which only apply in master mode (internal clock). given the desired baud rate and f osc , the nearest integer value for the spbrg register can be calculated using the formula in table 18-1. from this, the error in baud rate can be determined. example 18-1 shows the calculation of the baud rate error for the following conditions: f osc = 16 mhz desired baud rate = 9600 brgh = 0 sync = 0 it may be advantageous to use the high baud rate (brgh = 1 ), even for slower baud clocks, because the f osc /(16 (x + 1)) equation can reduce the baud rate error in some cases. writing a new value to the spbrg register causes the brg timer to be reset (or cleared). this ensures the brg does not wait for a timer overflow before outputting the new baud rate. 18.2.1 power managed mode operation the system clock is used to generate the desired baud rate; however, when a power managed mode is entered, the clock source may be operating at a differ- ent frequency than in pri_run mode. in sleep mode, no clocks are present and in pri_idle, the primary clock source continues to provide clocks to the baud rate generator; however, in other power managed modes, the clock frequency will probably change. this may require the value in spbrg to be adjusted. 18.2.2 sampling the data on the rc7/rx/dt pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rx pin. example 18-1: calculating baud rate error table 18-1: baud rate formula table 18-2: registers associated with baud rate generator sync brgh = 0 (low speed) brgh = 1 (high speed) 0 (asynchronous) 1 (synchronous) baud rate = f osc /(64 (x + 1)) baud rate = f osc /(4 (x + 1)) baud rate = f osc /(16 (x + 1)) n/a legend: x = value in spbrg (0 to 255) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. desired baud rate = f osc /(64 (x + 1)) solving for x: x = ((f osc /desired baud rate)/64) ? 1 x = ((16000000/9600)/64) ? 1 x = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desired baud rate) desired baud rate = (9615 ? 9600)/9600 = 0.16%
? 2003 microchip technology inc. ds39599c-page 199 pic18f2220/2320/4220/4320 table 18-3: baud rates for asynchronous mode (brgh = 0 , low speed) baud rate (k) f osc = 40.000 mhz f osc = 20.000 mhz f osc = 16.000 mhz f osc = 10.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 0.98 225.52 255 0.61 103.45 255 1.2 ? ? ? 1.22 1.73 255 1.20 0.16 207 1.20 0.16 129 2.4 2.44 1.73 255 2.40 0.16 129 2.40 0.16 103 2.40 0.16 64 9.6 9.62 0.16 64 9.47 -1.36 32 9.62 0.16 25 9.77 1.73 15 19.2 18.94 -1.36 32 19.53 1.73 15 19.23 0.16 12 19.53 1.73 7 38.4 39.06 1.73 15 39.06 1.73 7 35.71 -6.99 6 39.06 1.73 3 57.6 56.82 -1.36 10 62.50 8.51 4 62.50 8.51 3 52.08 -9.58 2 76.8 78.13 1.73 7 78.13 1.73 3 83.33 8.51 2 78.13 1.73 1 96.0 89.29 -6.99 6 104.17 8.51 2 ? ? ? ? ? ? 115.2 125.00 8.51 4 ? ? ? 125.00 8.51 1 78.13 -32.18 1 250.0 208.33 -16.67 2 ? ? 250.00 0.00 0 ? ? ? 300.0 312.50 4.17 1 312.50 4.17 0 ? ? ? ? ? ? 625.0 625.00 0.00 0 ? ? ? ? ? ? ? ? ? baud rate (k) f osc = 8.000000 mhz f osc = 7.159090 mhz f osc = 5.068800 mhz f osc = 4.000000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.49 62.76 255 0.44 45.65 255 0.31 3.13 255 0.30 0.16 207 1.2 1.20 0.16 103 1.20 0.23 92 1.20 0.00 65 1.20 0.16 51 2.4 2.40 0.16 51 2.38 -0.83 46 2.40 0.00 32 2.40 0.16 25 9.6 9.62 0.16 12 9.32 -2.90 11 9.90 3.13 7 8.93 -6.99 6 19.2 17.86 -6.99 6 18.64 -2.90 5 19.80 3.13 3 20.83 8.51 2 38.4 41.67 8.51 2 37.29 -2.90 2 39.60 3.13 1 31.25 -18.62 1 57.6 62.50 8.51 1 55.93 -2.90 1 ? ? ? 62.50 8.51 0 ? ? ? ? ? ? ? 79.20 3.13 0 ? ? ? 115.2 125.00 8.51 0 111.86 -2.90 0 ? ? ? ? ? ? baud rate (k) f osc = 3.579545 mhz f osc = 2.000000 mhz f osc = 1.000000 mhz f osc = 0.032768 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.30 0.23 185 0.30 0.16 103 0.30 0.16 51 0.26 -14.67 1 1.2 1.19 -0.83 46 1.20 0.16 25 1.20 0.16 12 ? ? ? 2.4 2.43 1.32 22 2.40 0.16 12 2.23 -6.99 6 ? ? ? 9.6 9.32 -2.90 5 10.42 8.51 2 7.81 -18.62 1 ? ? ? 19.2 18.64 -2.90 2 15.63 -18.62 1 15.63 -18.62 0 ? ? ? 38.4 ? ? ? 31.25 -18.62 0 ? ? ? ? ? ? 57.6 55.93 -2.90 0 ? ? ? ? ? ? ? ? ?
pic18f2220/2320/4220/4320 ds39599c-page 200 ? 2003 microchip technology inc. table 18-4: baud rates for asynchronous mode (brgh = 1 , high speed) baud rate (k) f osc = 40.000 mhz f osc = 20.000 mhz f osc = 16.000 mhz f osc = 10.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 2.4 ? ? ? 4.88 103.45 255 3.91 62.76 255 2.44 1.73 255 9.6 9.77 1.73 255 9.62 0.16 129 9.62 0.16 103 9.63 0.16 64 19.2 19.23 0.16 129 19.23 0.16 64 19.23 0.16 51 18.94 -1.36 32 38.4 38.46 0.16 64 37.88 -1.36 32 38.46 0.16 25 39.06 1.73 15 57.6 58.14 0.94 42 56.82 -1.36 21 58.82 2.12 16 56.82 -1.36 10 76.8 75.76 -1.36 32 78.13 1.73 15 76.92 0.16 12 78.13 1.73 7 96.0 96.15 0.16 25 96.15 0.16 12 100.00 4.17 9 89.29 -6.99 6 115.2 113.64 -1.36 21 113.64 -1.36 10 111.11 -3.55 8 125.00 8.51 4 250.0 250.00 0.00 9 250.00 0.00 4 250.00 0.00 3 208.33 -16.67 2 300.0 312.50 4.17 7 312.50 4.17 3 333.33 11.11 2 312.50 4.17 1 500.0 500.00 0.00 4 416.67 -16.67 2 500.00 0.00 1 ? ? ? 625.0 625.00 0.00 3 625.00 0.00 1 ? ? ? 625.00 0.00 0 1000.0 833.33 -16.67 2 ? ? ? 1000.00 0.00 0 ? ? ? 1250.0 1250.00 0.00 1 1250.00 0.00 0 ? ? ? ? ? ? baud rate (k) f osc = 8.000000 mhz f osc = 7.159090 mhz f osc = 5.068800 mhz f osc = 4.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? ? ? ? 0.98 225.52 255 1.2 1.95 62.76 255 1.75 45.65 255 1.24 3.13 255 1.20 0.16 207 2.4 2.40 0.16 207 2.41 0.23 185 2.40 0.00 131 2.40 0.16 103 9.6 9.62 0.16 51 9.52 -0.83 46 9.60 0.00 32 9.62 0.16 25 19.2 19.23 0.16 25 19.45 1.32 22 18.64 -2.94 16 19.23 0.16 12 38.4 38.46 0.16 12 37.29 -2.90 11 39.60 3.13 7 35.71 -6.99 6 57.6 55.56 -3.55 8 55.93 -2.90 7 52.80 -8.33 5 62.50 8.51 3 76.8 71.43 -6.99 6 74.57 -2.90 5 79.20 3.13 3 83.33 8.51 2 96.0 100.00 4.17 4 89.49 -6.78 4 ? ? ? ? ? ? 115.2 125.00 8.51 3 111.86 -2.90 3 105.60 -8.33 2 125.00 8.51 1 250.0 250.00 0.00 1 223.72 -10.51 1 ? ? ? 250.00 0.00 0 300.0 ? ? ? ? ? ? 316.80 5.60 0 ? ? ? 500.0 500.00 0.00 0 447.44 -10.51 0 ? ? ? ? ? ? baud rate (k) f osc = 3.579545 mhz f osc = 2.000000 mhz f osc = 1.000000 mhz f osc = 0.032768 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.87 191.30 255 0.49 62.76 255 0.30 0.16 207 0.29 -2.48 6 1.2 1.20 0.23 185 1.20 0.16 103 1.20 0.16 51 1.02 -14.67 1 2.4 2.41 0.23 92 2.40 0.16 51 2.40 0.16 25 2.05 -14.67 0 9.6 9.73 1.32 22 9.62 0.16 12 8.93 -6.99 6 ? ? ? 19.2 18.64 -2.90 11 17.86 -6.99 6 20.83 8.51 2 ? ? ? 38.4 37.29 -2.90 5 41.67 8.51 2 31.25 -18.62 1 ? ? ? 57.6 55.93 -2.90 3 62.50 8.51 1 62.50 8.51 0 ? ? ? 76.8 74.57 -2.90 2 ? ? ? ? ? ? ? ? ? 115.2 111.86 -2.90 1 125.00 8.51 0 ? ? ? ? ? ? 250.0 223.72 -10.51 0 ? ? ? ? ? ? ? ? ?
? 2003 microchip technology inc. ds39599c-page 201 pic18f2220/2320/4220/4320 table 18-5: baud rates for synchronous mode (sync = 1 ) baud rate (k) f osc = 40.000 mhz f osc = 20.000 mhz f osc = 16.000 mhz f osc = 10.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 9.6 ? ? ? ? ? ? 15.63 62.76 255 9.77 1.73 255 19.2 ? ? ? 19.53 1.73 255 19.23 0.16 207 19.23 0.16 129 38.4 39.06 1.73 255 38.46 0.16 129 38.46 0.16 103 38.46 0.16 64 57.6 57.47 -0.22 173 57.47 -0.22 86 57.97 0.64 68 58.14 0.94 42 76.8 76.92 0.16 129 76.92 0.16 64 76.92 0.16 51 75.76 -1.36 32 96.0 96.15 0.16 103 96.15 0.16 51 95.24 -0.79 41 96.15 0.16 25 250.0 250.00 0.00 39 250.00 0.00 19 250.00 0.00 15 250.00 0.00 9 300.0 303.03 1.01 32 294.12 -1.96 16 307.69 2.56 12 312.50 4.17 7 500.0 500.00 0.00 19 500.00 0.00 9 500.00 0.00 7 500.00 0.00 4 625.0 625.00 0.00 15 625.00 0.00 7 666.67 6.67 5 625.00 0.00 3 1000.0 1000.00 0.00 9 1000.00 0.00 4 1000.00 0.00 3 833.33 -16.67 2 1250.0 1250.00 0.00 7 1250.00 0.00 3 1333.33 6.67 2 1250.00 0.00 1 baud rate (k) f osc = 8.000000 mhz f osc = 7.159090 mhz f osc = 5.068800 mhz f osc = 4.000 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 2.4 7.81 225.52 255 6.99 191.30 255 4.95 106.25 255 3.91 62.76 255 9.6 9.62 0.16 207 9.62 0.23 185 9.60 0.00 131 9.62 0.16 103 19.2 19.23 0.16 103 19.24 0.23 92 19.20 0.00 65 19.23 0.16 51 38.4 38.46 0.16 51 38.08 -0.83 46 38.40 0.00 32 38.46 0.16 25 57.6 57.14 -0.79 34 57.73 0.23 30 57.60 0.00 21 58.82 2.12 16 76.8 76.92 0.16 25 77.82 1.32 22 74.54 -2.94 16 76.92 0.16 12 96.0 95.24 -0.79 20 94.20 -1.88 18 97.48 1.54 12 100.00 4.17 9 250.0 250.00 0.00 7 255.68 2.27 6 253.44 1.38 4 250.00 0.00 3 300.0 285.71 -4.76 6 298.30 -0.57 5 316.80 5.60 3 333.33 11.11 2 500.0 500.00 0.00 3 447.44 -10.51 3 422.40 -15.52 2 500.00 0.00 1 625.0 666.67 6.67 2 596.59 -4.55 2 633.60 1.38 1 ? ? ? 1000.0 1000.00 0.00 1 894.89 -10.51 1 ? ? ? 1000.00 0.00 0 1250.0 ? ? ? 1789.77 43.18 0 1267.20 1.38 0 ? ? ? baud rate (k) f osc = 3.579545 mhz f osc = 2.000000 mhz f osc = 1.000000 mhz f osc = 0.032768 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 0.98 225.52 255 0.30 1.14 26 1.2 ? ? ? 1.95 62.76 255 1.20 0.16 207 1.17 -2.48 6 2.4 3.50 45.65 255 2.40 0.16 207 2.40 0.16 103 2.73 13.78 2 9.6 9.62 0.23 92 9.62 0.16 51 9.62 0.16 25 8.19 -14.67 0 19.2 19.04 -0.83 46 19.23 0.16 25 19,.23 0.16 12 ? ? ? 38.4 38.91 1.32 22 38.46 0.16 12 35.71 -6.99 6 ? ? ? 57.6 55.93 -2.90 15 55.56 -3.55 8 62.50 8.51 3 ? ? ? 76.8 74.57 -2.90 11 71.43 -6.99 6 83.33 8.51 2 ? ? ? 96.0 99.43 3.57 8 100.00 4.17 4 ? ? ? ? ? ? 250.0 223.72 -10.51 3 250.00 0.00 1 250.00 0.00 0 ? ? ? 500.0 447.44 -10.51 1 500.00 0.00 0 ? ? ? ? ? ?
pic18f2220/2320/4220/4320 ds39599c-page 202 ? 2003 microchip technology inc. 18.3 usart asynchronous mode in this mode, the usart uses standard non-return- to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip dedicated 8-bit baud rate gener- ator can be used to derive standard baud rate frequen- cies from the oscillator. the usart transmits and receives the lsb first. the usart?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit brgh (txsta<2>). parity is not sup- ported by the hardware but can be implemented in soft- ware (and stored as the ninth data bit). asynchronous mode functions in all power managed modes except sleep mode when call clock sources are stopped. when in pri_idle mode, no changes to the baud rate generator values are required; however, other power managed mode clocks may operate at another frequency than the primary clock. therefore, the baud rate generator values may need adjusting. asynchronous mode is selected by clearing bit, sync (txsta<4>). the usart asynchronous module consists of the following important elements: baud rate generator sampling circuit asynchronous transmitter asynchronous receiver 18.3.1 usart asynchronous transmitter the usart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txreg register (if available). once the txreg register transfers the data to the tsr register (occurs in one t cy ), the txreg register is empty and flag bit, txif (pir1<4>), is set. this interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. flag bit txif is not cleared immediately upon loading the transmit buffer register, txreg. txif becomes valid in the second instruction cycle following the load instruction. polling txif immediately following a load of txreg will return invalid results. while flag bit txif indicated the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. status bit trmt is a read-only bit which is set when the tsr register is empty. no inter- rupt logic is tied to this bit, therefore, the user must poll this bit in order to determine whether the tsr register is empty. figure 18-1: usart transmit block diagram note 1: the tsr register is not mapped in data memory so it is not available to the user. 2: flag bit txif is set when enable bit txen is set. txif txie interrupt txen baud rate clk spbrg baud rate generator tx9d msb lsb data bus txreg register tsr register (8) 0 tx9 trmt spen rc6/tx/ck pin pin buffer and control 8 ? ? ?
? 2003 microchip technology inc. ds39599c-page 203 pic18f2220/2320/4220/4320 figure 18-2: asynchronous transmission figure 18-3: asynchronous transmission (back to back) table 18-6: registers associated with asynchronous transmission word 1 stop bit word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) rc6/tx/ck (pin) txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy transmit shift reg. write to txreg brg output (shift clock) rc6/tx/ck (pin) txif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic 18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 204 ? 2003 microchip technology inc. 18.3.2 usart asynchronous receiver the receiver block diagram is shown in figure 18-4. the data is received on the rc7/rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter oper- ates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. to set up an asynchronous reception: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 18.2 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit rcie. 4. if 9-bit reception is desired, set bit rx9. 5. enable the reception by setting bit cren. 6. flag bit rcif will be set when reception is com- plete and an interrupt will be generated if enable bit rcie was set. 7. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcreg register. 9. if any error occurred, clear the error by clearing enable bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 18.3.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is required, set the brgh bit. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if interrupts are required, set the rcen bit and select the desired priority level with the rcip bit. 4. set the rx9 bit to enable 9-bit reception. 5. set the adden bit to enable address detect. 6. enable reception by setting the cren bit. 7. the rcif bit will be set when reception is complete. the interrupt will be acknowledged if the rcie and gie bits are set. 8. read the rcsta register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. read rcreg to determine if the device is being addressed. 10. if any error occurred, clear the cren bit. 11. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. figure 18-4: usart receive block diagram x64 baud rate clk spbrg baud rate generator rc7/rx/dt pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ?
? 2003 microchip technology inc. ds39599c-page 205 pic18f2220/2320/4220/4320 to set up an asynchronous transmission: 1. initialize the spbrg register for the appropriate baud rate. if a high-speed baud rate is desired, set bit brgh ( section 18.2 ?usart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set transmit bit, tx9. can be used as address/data bit. 5. enable the transmission by setting bit txen which will also set bit txif. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. load data to the txreg register (starts transmission). 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-5: asynchronous reception table 18-7: registers associated with asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx (pin) reg rcv buffer reg rcv shift read rcv buffer reg rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx input. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ?brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 206 ? 2003 microchip technology inc. 18.4 usart synchronous master mode in synchronous master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit, sync (txsta<4>). in addition, enable bit, spen (rcsta<7>), is set in order to configure the rc6/tx/ck and rc7/rx/dt i/o pins to ck (clock) and dt (data) lines, respectively. the master mode indicates that the processor transmits the master clock on the ck line. the master mode is entered by setting bit, csrc (txsta<7>). 18.4.1 usart synchronous master transmission the usart transmitter block diagram is shown in figure 18-1. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txreg. the txreg register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txreg (if available). once the txreg register transfers the data to the tsr register (occurs in one t cycle ), the txreg is empty and inter- rupt bit, txif (pir1<4>), is set. the interrupt can be enabled/disabled by setting/clearing enable bit, txie (pie1<4>). flag bit txif will be set regardless of the state of enable bit txie and cannot be cleared in soft- ware. it will reset only when new data is loaded into the txreg register. while flag bit txif indicates the status of the txreg register, another bit, trmt (txsta<1>), shows the status of the tsr register. trmt is a read- only bit which is set when the tsr is empty. no inter- rupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrg register for the appropriate baud rate ( section 18.2 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-6: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx/dt rc6/tx/ck write to txreg reg txif bit (interrupt flag) trmt txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg = 0 ; continuous transmission of two 8-bit words. pin pin
? 2003 microchip technology inc. ds39599c-page 207 pic18f2220/2320/4220/4320 figure 18-7: synchronous transmissi on (through txen) table 18-8: registers associated with synchronous master transmission rc7/rx/dt pin rc6/tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 208 ? 2003 microchip technology inc. 18.4.2 usart synchronous master reception once synchronous mode is selected, reception is enabled by setting either enable bit, sren (rcsta<5>), or enable bit, cren (rcsta<4>). data is sampled on the rc7/rx/dt pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrg register for the appropriate baud rate ( section 18.2 ?usart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if interrupts are desired, set enable bit rcie. 5. if 9-bit reception is desired, set bit rx9. 6. if a single reception is required, set bit sren. for continuous reception, set bit cren. 7. interrupt flag bit rcif will be set when reception is complete and an interrupt will be generated if the enable bit rcie was set. 8. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcreg register. 10. if any error occurred, clear the error by clearing bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 18-8: synchronous reception (master mode, sren) table 18-9: registers associated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear. cren bit rc7/rx/dt pin rc6/tx/ck pin write to bit sren sren bit rcif bit (interrupt) read rxreg q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 .
? 2003 microchip technology inc. ds39599c-page 209 pic18f2220/2320/4220/4320 18.5 usart synchronous slave mode synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the rc6/tx/ck pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any power managed mode. slave mode is entered by clearing bit, csrc (txsta<7>). 18.5.1 usart synchronous slave transmit the operation of the synchronous master and slave modes are identical, except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in txreg register. c) flag bit txif will not be set. d) when the first word has been shifted out of tsr, the txreg register will transfer the second word to the tsr and flag bit txif will now be set. e) if enable bit txie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if interrupts are desired, set enable bit txie. 4. if 9-bit transmission is desired, set bit tx9. 5. enable the transmission by setting enable bit txen. 6. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 7. start transmission by loading data to the txreg register. 8. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-10: registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x txreg usart transmit register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: the pspif, pspie and pspip bits are reserved on the pic 18f2x20 devices; always maintain these bits clear.
pic18f2220/2320/4220/4320 ds39599c-page 210 ? 2003 microchip technology inc. 18.5.2 usart synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of sleep or any idle mode and bit sren, which is a ?don't care? in slave mode. if receive is enabled by setting bit cren prior to enter- ing sleep or any idle mode, then a word may be received while in this power managed mode. once the word is received, the rsr register will transfer the data to the rcreg register and if enable bit rcie bit is set, the interrupt generated will wake the chip from the power managed mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcie. 3. if 9-bit reception is desired, set bit rx9. 4. to enable reception, set enable bit cren. 5. flag bit rcif will be set when reception is complete. an interrupt will be generated if enable bit rcie was set. 6. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. read the 8-bit received data by reading the rcreg register. 8. if any error occurred, clear the error by clearing bit cren. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. table 18-11: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 0000 000u pir1 pspif (1) adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie (1) adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip (1) adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 -00x 0000 -00x rcreg usart receive register 0000 0000 0000 0000 txsta csrc tx9 txen sync ? brgh trmt tx9d 0000 -010 0000 -010 spbrg baud rate generator register 0000 0000 0000 0000 legend: x = unknown, - = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: the pspif, pspie and pspip bits are reserved on the pic18f2x20 devices; always maintain these bits clear.
? 2003 microchip technology inc. ds39599c-page 211 pic18f2220/2320/4220/4320 19.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 10 inputs for the pic18f2x20 devices and 13 for the pic18f4x20 devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. a new feature for the a/d converter is the addition of programmable acquisition time. this feature allows the user to select a new channel for conversion and setting the go/done bit immediately. when the go/done bit is set, the selected channel is sampled for the programmed acquisition time before a conversion is actually started. this removes the firmware overhead that may have been required to allow for an acquisition (sampling) period (see register 19-3 and section 19.3 ?selecting and configuring automatic acquisition time? ). the module has five registers: a/d result high register (adresh) a/d result low register (adresl) a/d control register 0 (adcon0) a/d control register 1 (adcon1) a/d control register 2 (adcon2) the adcon0 register, shown in register 19-1, controls the operation of the a/d module. the adcon1 register, shown in register 19-2, configures the functions of the port pins. the adcon2 register, shown in register 19-3, configures the a/d clock source, programmed acquisition time and justification. register 19-1: adcon0 register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-3 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) (1,2) 0110 = channel 6 (an6) (1,2) 0111 = channel 7 (an7) (1,2) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) 1101 = unimplemented (2) 1110 = unimplemented (2) 1111 = unimplemented (2) note 1: these channels are not implemented on the pic18f2x20 (28-pin) devices. 2: performing a conversion on unimplemented channels returns full-scale results. bit 1 go/done : a/d conversion status bit when adon = 1: 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 212 ? 2003 microchip technology inc. register 19-2: adcon1 register u-0 u-0 r/w-0 r/w-0 r/w-q (1) r/w-q (1) r/w-q (1) r/w-q (1) ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 vcfg1: voltage reference configuration bit, v refl source 1 =v ref - (an2) 0 =av ss bit 4 vcfg0: voltage reference configuration bit, v refh source 1 =v ref + (an3) 0 =av dd bit 3-0 pcfg3:pcfg0: a/d port configuration control bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown a = analog input d = digital i/o note 1: the por value of the pcfg bits depends on the value of the pbad bit in configuration register 3h. when pbad = 1 , pcfg<3:0> = 0000 ; when pbad = 0 , pcfg<3:0> = 0111 . 2: an5 through an7 are available only in pic18f4x20 devices. pcfg3: pcfg0 an12 an11 an10 an9 an8 an7 (2) an6 (2) an5 (2) an4 an3 an2 an1 an0 0000 (1) a a aaaaaaaaaaa 0001 a a aaaaaaaaaaa 0010 a a aaaaaaaaaaa 0011 d a aaaaaaaaaaa 0100 dd aaaaaaaaaaa 0101 dddaaaaaaaaaa 0110 ddddaaaaaaaaa 0111 (1) dddddaaaaaaaa 1000 ddddddaaaaaaa 1001 d d dddddaaaaaa 1010 d d ddddddaaaaa 1011 d d dddddddaaaa 1100 d d ddddddddaaa 1101 d d dddddddddaa 1110 d d dddddddddda 1111 d d ddddddddddd
? 2003 microchip technology inc. ds39599c-page 213 pic18f2220/2320/4220/4320 register 19-3: adcon2 register r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs1:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 214 ? 2003 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (av dd and av ss ), or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref -/cv ref pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh/adresl registers, the go/done bit (adcon0 register) is cleared and a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 19-1. figure 19-1: a/d block diagram (input voltage) v ain v refh reference voltage av dd vcfg1:vcfg0 chs3:chs0 an7 (1) an6 (1) an5 (1) an4 an3/v ref + an2/v ref - an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 v refl av ss an12 (2) an11 an10 an9 an8 1100 1011 1010 1001 1000 note 1: channels an5 through an7 are not available on pic18f2x20 devices. 2: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0 10-bit converter a/d
? 2003 microchip technology inc. ds39599c-page 215 pic18f2220/2320/4220/4320 the value in the adresh/adresl registers is not modified for a power-on reset. the adresh/ adresl registers will contain unknown data after a power-on reset. after the a/d module has been configured as desired, the selected channel must be acquired before the con- version is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 19.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: configure analog pins, voltage reference and digital i/o (adcon1) select a/d input channel (adcon0) select a/d acquisition time (adcon2) select a/d conversion clock (adcon2) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit set adie bit set gie bit 3. wait the required acquisition time (if required). 4. start conversion: set go/done bit (adcon0 register) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared or waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit adif if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. figure 19-2: analog input model v ain c pin rs anx 5 pf v dd v t = 0.6v v t = 0.6 v i leakage r ic 1k sampling switch ss r ss c hold = 120 pf v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss
pic18f2220/2320/4220/4320 ds39599c-page 216 ? 2003 microchip technology inc. 19.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the ana- log input model is shown in figure 19-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source imped- ance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k ? . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 19-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 19-1 shows the calculation of the minimum required acquisition time t acq . this calculation is based on the following application system assumptions: c hold = 120 pf r s = 2.5 k ? conversion error 1/2 lsb v dd =5v rss = 7 k ? temperature = 50 c (system max.) v hold = 0v @ time = 0 19.2 a/d v ref + and v ref - references if external voltage references are used instead of the internal av dd and av ss sources, the source imped- ance of the v ref + and v ref - voltage sources must be considered. during acquisition, currents supplied by these sources are insignificant. however, during con- version, the a/d module sinks and sources current through the reference sources. in order to maintain the a/d accuracy, the voltage ref- erence source impedances should be kept low to reduce voltage changes. these voltage changes occur as reference currents flow through the reference source impedance. the maximum recommended impedance of the v ref + and v ref - external reference voltage sources is 75 ? . equation 19-1: acquisition time equation 19-2: minimum a/d holding capacitor example 19-1: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. note: when using external references, the source impedance of the external voltage references must be less than 75 ? in order to achieve the specified adc resolution. a higher reference source impedance will increase the adc offset and gain errors. resistive voltage dividers will not provide a low enough source impedance. to ensure the best possible adc performance, exter- nal v ref inputs should be buffered with an op amp or other low-impedance circuit. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) (1 ? e (-tc/c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =5 s t coff =(temp ? 25 c)(0.05 s/ c) (50 c ? 25 c)(0.05 s/ c) 1.25 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 s. t c ? -(c hold )(r ic + r ss + r s ) ln(1/2047) s -(120 pf) (1 k ? + 7 k ? + 2.5 k ? ) ln(0.0004883) s 9.61 s t acq =5 s + 1.25 s + 9.61 s 12.86 s
? 2003 microchip technology inc. ds39599c-page 217 pic18f2220/2320/4220/4320 19.3 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state (? 000 ?) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module contin- ues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 19.4 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : 2 t osc 4 t osc 8 t osc 16 t osc 32 t osc 64 t osc internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad (approximately 2 s, see parameter #130 for more information). table 19-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 19-1: t ad vs. device operating frequencies ad clock source (t ad ) maximum device frequency operation adcs2:adcs0 pic18fxx20 pic18lfxx20 (4) 2 t osc 000 1.25 mhz 666 khz 4 t osc 100 2.50 mhz 1.33 mhz 8 t osc 001 5.00 mhz 2.66 mhz 16 t osc 101 10.0 mhz 5.33 mhz 32 t osc 010 20.0 mhz 10.65 mhz 64 t osc 110 40.0 mhz 21.33 mhz rc (3) x11 1.00 mhz (1) 1.00 mhz (2) note 1: the rc source has a typical t ad time of 4 s. 2: the rc source has a typical t ad time of 6 s. 3: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or the a/d accuracy may be out of specification. 4: low-power devices only.
pic18f2220/2320/4220/4320 ds39599c-page 218 ? 2003 microchip technology inc. 19.5 operation in power managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power managed mode. if the a/d is expected to operate while the device is in a power managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the power managed mode clock that will be used. after the power managed mode is entered (either of the power managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power managed mode clock source until the conversion has been com- pleted. if desired, the device may be placed into the corresponding power managed idle mode during the conversion. if the power managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d rc clock to be selected. if bits acqt2:acqt0 are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scs bits in the osccon register must have already been cleared prior to starting the conversion. 19.6 configuring analog port pins the adcon1, trisa, trisb and trise registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an ana- log input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits. 3: the pbaden bit in the configuration register configures portb pins to reset as analog or digital pins by controlling how the pcfg0 bits in adcon1 are reset.
? 2003 microchip technology inc. ds39599c-page 219 pic18f2220/2320/4220/4320 19.7 a/d conversions figure 19-3 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the follow- ing instruction to allow entry into sleep mode before the conversion begins. figure 19-4 shows the operation of the a/d converter after the go bit has been set and the acqt2:acqt0 bits are set to ? 010 ? and selecting a 4 t ad acquisition time before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. figure 19-3: a/d conversion t ad cycles (a cqt <2:0> = 000 , t acq = 0 ) figure 19-4: a/d conversion t ad cycles (a cqt <2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad next q4: adresh/adresl are loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl are loaded, go bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7
pic18f2220/2320/4220/4320 ds39599c-page 220 ? 2003 microchip technology inc. 19.8 use of the ccp2 trigger an a/d conversion can be started by the ?special event trigger? of the ccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/ done bit will be set, starting the a/d acquisition and conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automati- cally repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input chan- nel must be selected and the minimum acquisition period is either timed by the user or an appropriate t acq time, selected before the ?special event trigger?, sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the ?special event trigger? will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. table 19-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 0000 0000 0000 pir1 pspif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 pie1 pspie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 ipr1 pspip adip rcip txip sspip ccp1ip tmr2ip tmr1ip 1111 1111 1111 1111 pir2 oscfif cmif ? eeif bclif lvdif tmr3if ccp2if 00-0 0000 00-0 0000 pie2 oscfie cmie ? eeie bclie lvdie tmr3ie ccp2ie 00-0 0000 00-0 0000 ipr2 oscfip cmip ? eeip bclip lvdip tmr3ip ccp2ip 11-1 1111 11-1 1111 adresh a/d result register high byte xxxx xxxx uuuu uuuu adresl a/d result register low byte xxxx xxxx uuuu uuuu adcon0 ? ? chs3 chs3 chs1 chs0 go/done adon --00 0000 --00 0000 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 qqqq --00 qqqq adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 0-00 0000 porta ra7 (4) ra6 (4) ra5 ra4 ra3 ra2 ra1 ra0 --0x 0000 --0u 0000 trisa trisa7 (4) trisa6 (4) --11 1111 --11 1111 portb read portb pins, write latb latch xxxx xxxx uuuu uuuu trisb portb data direction register 1111 1111 1111 1111 latb portb output data latch xxxx xxxx uuuu uuuu porte ? ? ? ?re3 (2) read porte pins, write late (4) ---- xxxx ---- uuuu trise (3) ibf obe ibov pspmode ? porte data direction 0000 -111 0000 -111 late (3) ? ? ? ? porte output data latch ---- -xxx ---- -uuu legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition. shaded cells are not used for a/d conversion. note 1: re3 port bit is available only as an input pin w hen mclre bit in configuration register is ? 0 ?. 2: this register is not impl emented on pic18f2x20 devices. 3: these bits are not implemented on pic18f2x20 devices. 4: these pins may be configured as port pi ns depending on the oscillator mode selected.
? 2003 microchip technology inc. ds39599c-page 221 pic18f2220/2320/4220/4320 20.0 comparator module the comparator module contains two analog compara- tors. the inputs and outputs for the comparators are multiplexed with the ra0 through ra5 pins. the on- chip voltage reference ( section 21.0 ?comparator voltage reference module? ) can also be an input to the comparators. the cmcon register, shown as register 20-1, controls the comparator module?s input and output multiplexers. a block diagram of the various comparator configurations is shown in figure 20-1. 20.1 comparator configuration there are eight modes of oper ation for the comparators. the cm bits (cmcon<2:0>) are used to select these modes. figure 20-1 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in the electrical specifications (see section 26.0 ?electrical characteristics? ). register 20-1: cmcon register note: comparator interrupts should be disabled during a comparator mode change. otherwise, a false interrupt may occur. r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to ra3/an3 c2 v in - connects to ra2/an2 0 =c1 v in - connects to ra0/an0 c2 v in - connects to ra1/an1 bit 2-0 cm2:cm0 : comparator mode bits figure 20-1 shows the comparator modes and cm2:cm0 bit settings. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 222 ? 2003 microchip technology inc. figure 20-1: comparator i/o operating modes comparators reset cm<2:0> = 000 c1 ra0/an0 v in - v in + ra3/an3/ c1out two independent comparators a a cm<2:0> = 010 c2 ra1/an1 v in - v in + ra2/an2/ c2out a a c1 v in - v in + c1out two common reference comparators a a cm<2:0> = 100 c2 v in - v in + c2out a d c2 v in - v in + off (read as ? 0 ?) one independent comparator with output d d cm<2:0> = 001 c1 v in - v in + c1out a a c1 v in - v in + off (read as ? 0 ?) comparators off (por default value) d d cm<2:0> = 111 c2 v in - v in + off (read as ? 0 ?) d d c1 v in - v in + c1out four inputs multiplexed to two comparators a a cm<2:0> = 110 c2 v in - v in + c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs a a cm<2:0> = 101 c2 v in - v in + c2out a d a = analog input, port reads zeros always, overrides trisa bit (2) . d = digital input. cis (cmcon<3>) is the comparator input switch; cvroe (cvrcon<6>) is the voltage reference output switch. cv ref c1 v in - v in + c1out two independent comparators with outputs a a cm<2:0> = 011 c2 v in - v in + c2out a a ra4/t0cki/c1out (1) ra5/an4/ss /lvdin/c2out (1) ra4/t0cki/c1out (1) ra5/an4/ss /lvdin/c2out (1) ra4/t0cki/c1out (1) ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 ra0/an0 ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 ra3/an3/ ra1/an1 ra2/an2/ v ref + v ref -/cv ref v ref + v ref -/cv ref v ref + note 1: ra4 must be configured as an output pin in trisa<4> when used to output c1out. ra5 ignores trisa<5> when used as an output for c2out. 2: mode 110 is exception. comparator input pins obey trisa bits. v ref -/cv ref v ref -/cv ref cvroe = 1 cvroe = 0 v ref + v ref -/cv ref v ref + v ref + v ref -/cv ref v ref + v ref -/cv ref c1 v in - v in + off (r ead as ? 0 ?) d d c2 v in - v in + off (r ead as ? 0 ?) d d ra3/an3/ ra1/an1 ra2/an2/ ra0/an0 v ref + v ref -/cv ref
? 2003 microchip technology inc. ds39599c-page 223 pic18f2220/2320/4220/4320 20.2 comparator operation a single comparator is shown in figure 20-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 20-2 represent the uncertainty due to input offsets and response time. 20.3 comparator reference an external or internal reference signal may be used depending on the comparator operating mode. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 20-2). figure 20-2: single comparator 20.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 20.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the compara- tors. section 21.0 ?comparator voltage reference module? contains a detailed description of the compar- ator voltage reference module that provides this signal. the internal reference signal is used when comparators are in mode, cm2:cm0 = 110 (figure 20-1). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. depending on the setting of the cvroe bit (cvrcon<6>), the voltage reference may also be available on pin ra2. 20.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see table 26-2 in section 26.0 ?electrical characteristics? ). 20.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the ra4 and ra5 i/o pins. when enabled, multiplexers in the output path of the ra4 and ra5 pins will switch and the output of each pin will be the unsynchronized output of the com- parator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 20-3 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra4 and ra5 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<4:5>). ? + v in + v in - output v in? v in+ o utput output v in + v in - note 1: when reading the port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
pic18f2220/2320/4220/4320 ds39599c-page 224 ? 2003 microchip technology inc. figure 20-3: comparator output block diagram 20.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir registers) is the comparator interrupt flag. the cmif bit is cleared by firmware. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. the cmie bit (pie registers) and the peie bit (intcon register) must be set to enable the interrupt. in addition, the gie bit must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. d q en to ra4 or ra5 pin bus data read cmcon set multiplex cmif bit - + d q en cl port pins read cmcon reset from other comparator cxinv note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir registers) interrupt flag may not get set.
? 2003 microchip technology inc. ds39599c-page 225 pic18f2220/2320/4220/4320 20.7 comparator operation in power managed modes when a comparator is active and the device is placed in a power managed mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake-up the device from a power managed mode when enabled. each operational com- parator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in a power managed mode, turn off the comparators (cm<2:0> = 111 ) before entering the power managed modes. if the device wakes up from a power managed mode, the contents of the cmcon register are not affected. 20.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator module to be in the com- parator reset mode (cm<2:0> = 111) . this ensures that all potential inputs are analog inputs. device cur- rent is minimized when digital inputs are present at reset time. the comparators will be powered down during the reset interval. 20.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 20-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . therefore, the analog input must be between v ss and v dd . if the input voltage exceeds this range by more than 0.6v, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. figure 20-4: comparator analog input model va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input
pic18f2220/2320/4220/4320 ds39599c-page 226 ? 2003 microchip technology inc. table 20-1: registers associated with comparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 intcon gie/ gieh peie/ giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 0000 0000 0000 pir2 ?cmif ? ? bclif lvdif tmr3if ccp2if -0-- 0000 -0-- 0000 pie2 ?cmie ? ? bclie lvdie tmr3ie ccp2ie -0-- 0000 -0-- 0000 ipr2 ?cmip ? ? bclip lvdip tmr3ip ccp2ip -1-- 1111 -1-- 1111 porta ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 xx0x 0000 xx0x 0000 lata ? ? lata data output register xxxx xxxx xxxx xxxx trisa ? ? porta data direction register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are unused by the comparator module. note 1: these pins are enabled based on oscillator configuration (see configuration register 1h).
? 2003 microchip technology inc. ds39599c-page 227 pic18f2220/2320/4220/4320 21.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable voltage refer- ence. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down func- tion to conserve power when the reference is not being used. the cvrcon register controls the operation of the reference as shown in register 21-1. the block diagram is given in figure 21-1. the comparator reference supply voltage comes from v dd and v ss . 21.1 configuring the comparator voltage reference the comparator voltage reference can output 16 distinct voltage levels for each range. the equations used to cal- culate the output of the comparator voltage reference are as follows: equation 21-1: the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 26-2 in section 26.0 ?electrical characteristics? ). register 21-1: cvrcon register if cvrr = 1 : cv ref = (cvr<3:0>) ? if cvrr = 0 : cv ref = (cvr<3:0> + 8) ? v dd 24 v dd 32 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit 1 =cv ref voltage level is also output on the ra2/an2/v ref -/cv ref (1) pin 0 =cv ref voltage is disconnected from the ra2/an2/v ref -/cv ref pin note 1: cvroe overrides the trisa<2> bit setting. bit 5 cvrr : comparator v ref range selection bit 1 = 0.00 v dd to 0.75 v dd , with v dd /24 step size 0 = 0.25 v dd to 0.75 v dd , with v dd /32 step size bit 4 unimplemented: read as ? 0 ? bit 3-0 cvr3:cvr0: comparator v ref value selection 0 vr3:vr0 15 bits when cvrr = 1 : cv ref = (cvr<3:0>) ? when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr<3:0> + 8) ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown v dd 24 v dd 32
pic18f2220/2320/4220/4320 ds39599c-page 228 ? 2003 microchip technology inc. figure 21-1: voltage reference block diagram 21.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 21-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from v dd ; therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the voltage reference can be found in section 26.0 ?electrical characteristics? . 21.3 operation in power managed modes the contents of the cvrcon register are not affected by entry to or exit from power managed modes. to min- imize current consumption in power managed modes, the voltage reference module should be disabled; how- ever, this can cause an interrupt from the comparators so the comparator interrupt should also be disabled while the cvrcon register is being modified. 21.4 effects of a reset a device reset disables the voltage reference by clear- ing the cvrcon register. this also disconnects the reference from the ra2 pin, selects the high-voltage range and selects the lowest voltage tap from the resistor divider. 21.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be output using the ra2 pin if the cvroe bit is set. enabling the voltage reference out- put onto the ra2 pin, with an input signal present, will increase current consumption. the ra2 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, an external buffer must be used on the voltage reference output for external connections to v ref . figure 21-2 shows an example buffering technique. 8r cvr3 cvr0 (from cvrcon<3:0>) 16-1 analog mux 8r r r r r cvren cv ref 16 stages v dd cvrr cvroe ra2/an2/v ref -/cv ref
? 2003 microchip technology inc. ds39599c-page 229 pic18f2220/2320/4220/4320 figure 21-2: voltage reference output buffer example table 21-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) ra2 note 1: r is dependent upon the voltage reference configuration bits (cvrcon<3:0> and cvrcon<5>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por value on all other resets cvrcon cvren cvroe cvrr ? cvr3 cvr2 cvr1 cvr0 000- 0000 000- 0000 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 0000 0111 trisa ra7 (1) ra6 (1) ra5 ra4 ra3 ra2 ra1 ra0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference. note 1: these pins are enabled based on oscillator configuration (see configuration register 1h).
pic18f2220/2320/4220/4320 ds39599c-page 230 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 231 pic18f2220/2320/4220/4320 22.0 low-voltage detect in many applications, the ability to determine if the device voltage (v dd ) is below a specified voltage level is a desirable feature. a window of operation for the application can be created, where the application soft- ware can do ?housekeeping tasks? before the device voltage exits the valid operating range. this can be done using the low-voltage detect (lvd) module. this module is a software programmable circuitry, where a device voltage trip point can be specified. when the voltage of the device becomes lower then the specified point, an interrupt flag is set. if the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to that interrupt source. the low-voltage detect circuitry is completely under software control. this allows the circuitry to be turned off by the software which minimizes the current consumption for the device. figure 22-1 shows a possible application voltage curve (typically for batteries). over time, the device voltage decreases. when the device voltage equals voltage v a , the lvd logic generates an interrupt. this occurs at time t a . the application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. voltage point v b is the minimum valid operating voltage specification. this occurs at time t b . the difference, t b ? t a , is the total time for shutdown. the block diagram for the lvd module is shown in figure 22-2. a comparator uses an internally gener- ated reference voltage as the set point. when the selected tap output of the device voltage crosses the set point (is lower than), the lvdif bit is set. each node in the resistor divider represents a ?trip point? voltage. the ?trip point? voltage is the minimum supply voltage level at which the device can operate before the lvd module asserts an interrupt. when the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2v internal reference voltage generated by the voltage ref- erence module. the comparator then generates an interrupt signal setting the lvdif bit. this voltage is software programmable to any one of 16 values (see figure 22-2). the trip point is selected by programming the lvdl3:lvdl0 bits (lvdcon<3:0>). figure 22-1: typical low-voltage detect application time voltage v a v b t a t b v a = lvd trip point v b = minimum valid device operating voltage legend:
pic18f2220/2320/4220/4320 ds39599c-page 232 ? 2003 microchip technology inc. figure 22-2: low-voltage detect (lvd) block diagram the lvd module has an additional feature that allows the user to supply the sense voltage to the module from an external source. this mode is enabled when bits lvdl3:lvdl0 are set to ? 1111 ?. in this state, the comparator input is multiplexed from the external input pin, lvdin (figure 22-3). this gives users flexibility because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. figure 22-3: low-voltage detect (lvd) with external input block diagram lvdif v dd 16 to 1 mux lvden lvd control register internally generated reference voltage lvdin 1.2v lvd en lvd control 16 to 1 mux bgap boden lvden vxen lvdin register v dd v dd externally generated trip point
? 2003 microchip technology inc. ds39599c-page 233 pic18f2220/2320/4220/4320 22.1 control register the low-voltage detect control register controls the operation of the low-voltage detect circuitry. register 22-1: lvdcon register u-0 u-0 r-0 r/w-0 r/w-0 r/w-1 r/w-0 r/w-1 ? ? irvst lvden lvdl3 lvdl2 lvdl1 lvdl0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5 irvst: internal reference voltage stable flag bit 1 = indicates that the low-voltage detect logic will generate the interrupt flag at the specified voltage range 0 = indicates that the low-voltage detect logic will not generate the interrupt flag at the specified voltage range and the lvd interrupt should not be enabled bit 4 lvden: low-voltage detect power enable bit 1 = enables lvd, powers up lvd circuit 0 = disables lvd, powers down lvd circuit bit 3-0 lvdl3:lvdl0: low-voltage detection limit bits 1111 = external analog input is used (input comes from the lvdin pin) 1110 = 4.50v-4.78v 1101 = 4.20v-4.46v 1100 = 4.00v-4.26v 1011 = 3.80v-4.04v 1010 = 3.60v-3.84v 1001 = 3.50v-3.72v 1000 = 3.30v-3.52v 0111 = 3.00v-3.20v 0110 = 2.80v-2.98v 0101 = 2.70v-2.86v 0100 = 2.50v-2.66v 0011 = 2.40v-2.55v 0010 = 2.20v-2.34v 0001 = 2.00v-2.12v 0000 = reserved note: lvdl3:lvdl0 modes which result in a trip point below the valid operating voltage of the device are not tested. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
pic18f2220/2320/4220/4320 ds39599c-page 234 ? 2003 microchip technology inc. 22.2 operation depending on the power source for the device voltage, the voltage normally decreases relatively slowly. this means that the lvd module does not need to be constantly operating. to decrease the current require- ments, the lvd circuitry only needs to be enabled for short periods where the voltage is checked. after doing the check, the lvd module may be disabled. each time that the lvd module is enabled, the circuitry requires some time to stabilize. after the circuitry has stabilized, all status flags may be cleared. the module will then indicate the proper state of the system. the following steps are needed to set up the lvd module: 1. write the value to the lvdl3:lvdl0 bits (lvdcon register) which selects the desired lvd trip point. 2. ensure that lvd interrupts are disabled (the lvdie bit is cleared or the gie bit is cleared). 3. enable the lvd module (set the lvden bit in the lvdcon register). 4. wait for the lvd module to stabilize (the irvst bit to become set). 5. clear the lvd interrupt flag, which may have falsely become set, until the lvd module has stabilized (clear the lvdif bit). 6. enable the lvd interrupt (set the lvdie and the gie bits). figure 22-4 shows typical waveforms that the lvd module may be used to detect. figure 22-4: low-voltage detect waveforms v lvd v dd lvdif v lvd v dd enable lvd internally generated t ivrst lvdif may not be set enable lvd lvdif lvdif cleared in software lvdif cleared in software lvdif cleared in software, case 1: case 2: lvdif remains set since lvd condition still exists reference stable internally generated reference stable t ivrst
? 2003 microchip technology inc. ds39599c-page 235 pic18f2220/2320/4220/4320 22.2.1 reference voltage set point the internal reference voltage of the lvd module may be used by other internal circuitry (the programmable brown-out reset). if these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. this time is invariant of system clock speed. this start-up time is specified in electrical specification parameter #36. the low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. refer to the waveform in figure 22-4. 22.2.2 current consumption when the module is enabled, the lvd comparator and voltage divider are enabled and will consume static cur- rent. the voltage divider can be tapped from multiple places in the resistor array. total current consumption, when enabled, is specified in electrical specification parameter #d022b. 22.3 operation during sleep when enabled, the lvd circuitry continues to operate during sleep. if the device voltage crosses the trip point, the lvdif bit will be set and the device will wake- up from sleep. device execution will continue from the interrupt vector address if interrupts have been globally enabled. 22.4 effects of a reset a device reset forces all registers to their reset state. this forces the lvd module to be turned off.
pic18f2220/2320/4220/4320 ds39599c-page 236 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 237 pic18f2220/2320/4220/4320 23.0 special features of the cpu pic18f2x20/4x20 devices include several features intended to maximize system reliability and minimize cost through elimination of external components. these are: oscillator selection resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) fail-safe clock monitor two-speed start-up code protection id locations in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, pic18f2x20/4x20 devices have a watchdog timer which is either perma- nently enabled via the configuration bits or software controlled (if configured as disabled). the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two- speed start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 23.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these bits are mapped starting at program memory location 300000h. the user will note that address 300000h is beyond the user program memory space. in fact, it belongs to the configuration memory space (300000h-3fffffh) which can only be accessed using table reads and table writes. programming the configuration registers is done in a manner similar to programming the flash memory. the eecon1 register wr bit starts a self-timed write to the configuration register. in normal operation mode, a tblwt instruction with the tblptr pointing to the con- figuration register sets up the address and the data for the configuration register write. setting the wr bit starts a long write to the configuration register. the con- figuration registers are written a byte at a time. to write or erase a configuration cell, a tblwt instruction can write a ? 1 ? or a ? 0 ? into the cell. for additional details on flash programming, refer to section 6.5 ?writing to flash program memory? . table 23-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 300001h config1h ieso fscm ? ?f osc 3f osc 2f osc 1f osc 0 11-- 1111 300002h config2l ? ? ? ? borv1 borv0 bor pwrt ---- 1111 300003h config2h ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdt ---1 1111 300005h config3h mclre ? ? ? ? ?pbadccp2mx 1--- --11 300006h config4l debug ? ? ? ?lvp ?stvr 1--- -1-1 300008h config5l ? ? ? ? cp3 cp2 cp1 cp0 ---- 1111 300009h config5h cpd cpb ? ? ? ? ? ? 11-- ---- 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 ---- 1111 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 111- ---- 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 ---- 1111 30000dh config7h ?ebtrb ? ? ? ? ? ? -1-- ---- 3ffffeh devid1 (1) dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (1) 3fffffh devid2 (1) dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 0000 0101 legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. shaded cells are unimplemented, read as ? 0 ?. note 1: see register 23-14 for devid1 values. devid regist ers are read-only and cannot be programmed by the user.
pic18f2220/2320/4220/4320 ds39599c-page 238 ? 2003 microchip technology inc. register 23-1: config1h: configuration register 1 high (byte address 300001h) r/p-1 r/p-1 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ieso fscm ? ?f osc 3f osc 2f osc 1f osc 0 bit 7 bit 0 bit 7 ieso: internal external switch over bit 1 = internal external switch over mode enabled 0 = internal external switch over mode disabled bit 6 fscm: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-4 unimplemented: read as ? 0 ? bit 3-0 f osc <3:0>: oscillator selection bits 11xx = external rc oscillator, clko function on ra6 1001 = internal oscillator block, clko function on ra6 and port function on ra7 1000 = internal oscillator block, port function on ra6 and port function on ra7 0111 = external rc oscillator, port function on ra6 0110 = hs oscillator, pll enabled (clock frequency = 4 x f osc 1) 0101 = ec oscillator, port function on ra6 0100 = ec oscillator, clko function on ra6 0010 = hs oscillator 0001 = xt oscillator 0000 = lp oscillator legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 2003 microchip technology inc. ds39599c-page 239 pic18f2220/2320/4220/4320 register 23-2: config2l: configuration register 2 low (byte address 300002h) register 23-3: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? borv1 borv0 bor pwrt bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3-2 borv1:borv0: brown-out reset voltage bits 11 = v bor set to 2.0v 10 = v bor set to 2.7v 01 = v bor set to 4.2v 00 = v bor set to 4.5v bit 1 bor: brown-out reset enable bit (1) 1 = brown-out reset enabled 0 = brown-out reset disabled bit 0 pwrt : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled note 1: the power-up timer is decoupled from brown-out reset, allowing these features to be independently controlled. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 wdt bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdps<3:0>: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 0 wdt: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on the swdten bit) legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
pic18f2220/2320/4220/4320 ds39599c-page 240 ? 2003 microchip technology inc. register 23-4: config3h: configuration register 3 high (byte address 300005h) register 23-5: config4l: configuration register 4 low (byte address 300006h) r/p-1 u-0 u-0 u-0 u-0 u-0 r/p-1 r/p-1 mclre ? ? ? ? ? pbad ccp2mx bit 7 bit 0 bit 7 mclre: mclr pin enable bit 1 = mclr pin enabled; re3 input pin disabled 0 = re3 input pin enabled; mclr disabled bit 6-2 unimplemented: read as ? 0 ? bit 1 pbad: portb a/d enable bit (affects adcon1 reset state. adcon1 controls portb<4:0> pin configuration.) 1 = portb<4:0> pins are configured as analog input channels on reset 0 = portb<4:0> pins are configured as digital i/o on reset bit 0 ccp2mx: ccp2 mux bit 1 = ccp2 input/output is multiplexed with rc1 0 = ccp2 input/output is multiplexed with rb3 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state r/p-1 u-0 u-0 u-0 u-0 r/p-1 u-0 r/p-1 debug ? ? ? ?lvp ?stvr bit 7 bit 0 bit 7 debug : background debugger enable bit 1 = background debugger disabled, rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled, rb6 and rb7 are dedicated to in-circuit debug bit 6-3 unimplemented: read as ? 0 ? bit 2 lvp: low-voltage icsp enable bit 1 = low-voltage icsp enabled 0 = low-voltage icsp disabled bit 1 unimplemented: read as ? 0 ? bit 0 stvr: stack full/underflow reset enable bit 1 = stack full/underflow will cause reset 0 = stack full/underflow will not cause reset legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 2003 microchip technology inc. ds39599c-page 241 pic18f2220/2320/4220/4320 register 23-6: config5l: configuration register 5 low (byte address 300008h) register 23-7: config5h: configuration register 5 high (byte address 300009h) u-0 u-0 u-0 u-0 r/c-1 r/c-1 r/c-1 r/c-1 ? ? ? ?cp3 (1) cp2 (1) cp1 cp0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 cp3: code protection bit (1) 1 = block 3 (001800-001fffh) not code-protected 0 = block 3 (001800-001fffh) code-protected bit 2 cp2: code protection bit (1) 1 = block 2 (001000-0017ffh) not code-protected 0 = block 2 (001000-0017ffh) code-protected bit 1 cp1: code protection bit 1 = block 1 (000800-000fffh) not code-protected 0 = block 1 (000800-000fffh) code-protected bit 0 cp0: code protection bit 1 = block 0 (000200-0007ffh) not code-protected 0 = block 0 (000200-0007ffh) code-protected note 1: unimplemented in pic18fx220 devices; maintain this bit set. legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state r/c-1 r/c-1 u-0 u-0 u-0 u-0 u-0 u-0 cpd cpb ? ? ? ? ? ? bit 7 bit 0 bit 7 cpd: data eeprom code protection bit 1 = data eeprom not code-protected 0 = data eeprom code-protected bit 6 cpb: boot block code protection bit 1 = boot block (000000-0001ffh) not code-protected 0 = boot block (000000-0001ffh) code-protected bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
pic18f2220/2320/4220/4320 ds39599c-page 242 ? 2003 microchip technology inc. register 23-8: config6l: configuration register 6 low (byte address 30000ah) register 23-9: config6h: co nfiguration register 6 high (byte address 30000bh) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ?wrt3 (1) wrt2 (1) wrt1 wrt0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 wrt3: write protection bit (1) 1 = block 3 (001800-001fffh) not write-protected 0 = block 3 (001800-001fffh) write-protected bit 2 wrt2: write protection bit (1) 1 = block 2 (001000-0017ffh) not write-protected 0 = block 2 (001000-0017ffh) write-protected bit 1 wrt1: write protection bit 1 = block 1 (000800-000fffh) not write-protected 0 = block 1 (000800-000fffh) write-protected bit 0 wrt0: write protection bit 1 = block 0 (000200-0007ffh) not write-protected 0 = block 0 (000200-0007ffh) write-protected note 1: unimplemented in pic18fx220 devices; maintain this bit set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state r/p-1 r/p-1 r-1 u-0 u-0 u-0 u-0 u-0 wrtd wrtb wrtc ? ? ? ? ? bit 7 bit 0 bit 7 wrtd: data eeprom write protection bit 1 = data eeprom not write-protected 0 = data eeprom write-protected bit 6 wrtb: boot block write protection bit 1 = boot block (000000-0001ffh) not write-protected 0 = boot block (000000-0001ffh) write-protected bit 5 wrtc: configuration register write protection bit 1 = configuration registers (300000-3000ffh) not write-protected 0 = configuration registers (300000-3000ffh) write-protected note: this bit is read-only in normal execution mode; it can be written only in program mode. bit 4-0 unimplemented: read as ? 0 ? legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 2003 microchip technology inc. ds39599c-page 243 pic18f2220/2320/4220/4320 register 23-10: config7l: configuration register 7 low (byte address 30000ch) register 23-11: config7h: configuration register 7 high (byte address 30000dh) u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? ebtr3 (1) ebtr2 (1) ebtr1 ebtr0 bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 ebtr3: table read protection bit (1) 1 = block 3 (001800-001fffh) not protected from table reads executed in other blocks 0 = block 3 (001800-001fffh) protected from table reads executed in other blocks bit 2 ebtr2: table read protection bit (1) 1 = block 2 (001000-0017ffh) not protected from table reads executed in other blocks 0 = block 2 (001000-0017ffh) protected from table reads executed in other blocks bit 1 ebtr1: table read protection bit 1 = block 1 (000800-000fffh) not protected from table reads executed in other blocks 0 = block 1 (000800-000fffh) protected from table reads executed in other blocks bit 0 ebtr0: table read protection bit 1 = block 0 (000200-0007ffh) not protected from table reads executed in other blocks 0 = block 0 (000200-0007ffh) protected from table reads executed in other blocks note 1: unimplemented in pic18fx220 devices; maintain this bit set. legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state u-0 r/p-1 u-0 u-0 u-0 u-0 u-0 u-0 ? ebtrb ? ? ? ? ? ? bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6 ebtrb: boot block table read protection bit 1 = boot block (000000-0001ffh) not protected from table reads executed in other blocks 0 = boot block (000000-0001ffh) protected from table reads executed in other blocks bit 5-0 unimplemented: read as ? 0 ? legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
pic18f2220/2320/4220/4320 ds39599c-page 244 ? 2003 microchip technology inc. register 23-12: device id register 1 for pic18f2220/2320/4220/4320 devices register 23-13: device id register 2 for pic18f2220/2320/4220/4320 devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 bit 7-5 dev2:dev0: device id bits 000 = pic18f4220 001 = pic18f4320 100 = pic18f2220 101 = pic18f2320 bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 bit 7-0 dev10:dev3: device id bits these bits are used with the dev2:dev0 bits in the device id register 1 to identify the part number. 0000 0101 = pic18f2220/2320/4220/4320 devices note: these values for dev10:dev3 may be shared with other devices. the specific device is always identified by using the entire dev10:dev0 bit sequence. legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? - n = value when device is unprogrammed u = unchanged from programmed state
? 2003 microchip technology inc. ds39599c-page 245 pic18f2220/2320/4220/4320 23.2 watchdog timer (wdt) for pic18f2x20/4x20 devices, the wdt is driven by the intrc source. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexer, controlled by bits in configu- ration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared when any of the following events occur: execute a sleep or clrwdt instruction, the ircf bits (osccon<6:4>) are changed or a clock failure has occurred. adjustments to the internal oscillator clock period using the osctune register also affect the period of the wdt by the same factor. for example, if the intrc period is increased by 3%, then the wdt period is increased by 3%. 23.2.1 control register register 23-14 shows the wdtcon register. this is a readable and writable register which contains a control bit that allows software to override the wdt enable configuration bit, but only if the configuration bit has disabled the wdt. figure 23-1: wdt block diagram note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: changing the setting of the ircf bits (osccon<6:4> clears the wdt and postscaler counts. 3: when a clrwdt instruction is executed, the postscaler count will be cleared. intrc source wdt wake-up reset wdt wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps<3:0> swdten wdten clrwdt 4 from sleep reset all device resets sleep intrc control 125 change on ircf bits
pic18f2220/2320/4220/4320 ds39599c-page 246 ? 2003 microchip technology inc. register 23-14: wdtcon register table 23-2: summary of watchdog timer registers u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten bit 7 bit 0 bit 7-1 unimplemented : read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit 1 = watchdog timer is on 0 = watchdog timer is off note 1: this bit has no effect if the configuration bit, wdten (config2h<0>), is enabled. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 config2h ? ? ? wdtps3 wdtps2 wdtps2 wdtps0 wdten rcon ipen ? ? ri to pd por bor wdtcon ? ? ? ? ? ? ?swdten legend: shaded cells are not used by the watchdog timer.
? 2003 microchip technology inc. ds39599c-page 247 pic18f2220/2320/4220/4320 23.3 two-speed start-up the two-speed start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the intrc oscil- lator as a clock source until the primary clock source is available. it is enabled by setting the ieso bit in configuration register 1h (config1h<7>). two-speed start-up is availabl e only if the primary oscil- lator mode is lp, xt, hs or hspll (crystal-based modes). other sources do not require a ost start-up delay; for these, two-speed start-up is disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the inter- nal oscillator block as the clock source, following the time-out of the power-up timer after a por reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is run- ning. once the ost times out, the device automatically switches to pri_run mode. because the osccon register is cleared on reset events, the intosc (or postscaler) clock source is not initially available after a reset event; the intrc clock is used directly at its base frequency. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits ifrc2:ifrc0 immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting ifrc2:ifrc0 prior to entering sleep mode. in all other power managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 23.3.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start-up, the device still obeys the normal command sequences for entering power managed modes, including serial sleep instructions (refer to section 3.1.3 ?multiple sleep commands? ). in practice, this means that user code can change the scs1:scs0 bit settings and issue sleep commands before the ost times out. this would allow an application to briefly wake-up, perform routine ?housekeeping? tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the system clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the system clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 23-2: timing transition for two-speed start-up (intosc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intosc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 q4 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t ost (1) t pll (1) 12 3 45678 clock transition osts bit set multiplexer
pic18f2220/2320/4220/4320 ds39599c-page 248 ? 2003 microchip technology inc. 23.4 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the micro- controller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. the fscm function is enabled by setting the fail-safe clock monitor enable bit, fcmen (config1h<6>). when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. clock monitoring (shown in figure 23-3) is accom- plished by creating a sample clock signal, which is the intrc output divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral system clock and the sample clock are presented as inputs to the clock mon- itor latch (cm). the cm is set on the falling edge of the system clock source but cleared on the rising edge of the sample clock. figure 23-3: fscm block diagram clock failure is tested on the falling edge of the sample clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 23-4). this causes the following: the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>) the system clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source ? this is the fail-safe condition) the wdt is reset since the postscaler frequency from the internal oscil- lator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power managed mode (see section 23.3.1 ?special considerations for using two-speed start-up? and section 3.1.3 ?multiple sleep commands? for more details). this can be done to attempt a partial recovery or execute a controlled shutdown. to use a higher clock speed on wake-up, the intosc or postscaler clock sources can be selected to provide a higher clock speed by setting bits ifrc2:ifrc0 immediately after reset. for wake-ups from sleep, the intosc or postscaler clock sources can be selected by setting ifrc2:ifrc0 prior to entering sleep mode. adjustments to the internal oscillator block using the osctune register also affect the period of the fscm by the same factor. this can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. the fscm will detect failures of the primary or second- ary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 23.4.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a sep- arate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intosc clock when a clock failure is detected. depending on the frequency selected by the ircf2:ircf0 bits, this may mean a substantial change in the speed of code execution. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock events also reset the wdt and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. peripheral intrc 64 s c q (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q
? 2003 microchip technology inc. ds39599c-page 249 pic18f2220/2320/4220/4320 23.4.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power managed mode. on reset, the controller starts the primary clock source specified in configuration register 1h (with any required start-up delays that are required for the oscillator mode, such as ost or pll timer). the intosc multiplexer provides the system clock until the primary clock source becomes ready (similar to a two-speed start-up). the clock system source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready dur- ing start-up. in this case, operation is clocked by the intosc multiplexer. the osccon register will remain in its reset state until a power managed mode is entered. entering a power managed mode by loading the osccon register and executing a sleep instruction will clear the fail-safe condition. when the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. figure 23-4: fscm timing diagram oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequenc y than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test
pic18f2220/2320/4220/4320 ds39599c-page 250 ? 2003 microchip technology inc. 23.4.3 fscm interrupts in power managed modes as previously mentioned, entering a power managed mode clears the fail-safe condition. by entering a power managed mode, the clock multiplexer selects the clock source selected by the osccon register. fail-safe monitoring of the power managed clock source resumes in the power managed mode. if an oscillator failure occurs during power managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intosc multiplexer. an automatic transition back to the failed clock source will not occur. if the interrupt is disabled, the device will not exit the power managed mode on oscillator failure. instead, the device will continue to operate as before but clocked by the intosc multiplexer. while in idle mode, subse- quent interrupts will cause the cpu to begin executing instructions while being clocked by the intosc multi- plexer. the device will not transition to a different clock source until the fail-safe condition is cleared. 23.4.4 por or wake from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary system clock is ec, rc or intrc modes, monitoring can begin immediately following these events. for oscillator modes involving a crystal or resonator (hs, hspll, lp or xt), the situation is somewhat dif- ferent. since the oscillator may require a start-up time considerably longer than the fcsm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 23.3.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alter- nate power managed mode while waiting for the pri- mary system clock to become stable. when the new powered managed mode is selected, the primary clock is disabled. note: the same logic that prevents false oscilla- tor failure interrupts on por or wake from sleep will also prevent the detection of the oscillator?s failure to start at all following these events. this can be avoided by monitoring the osts bit and using a tim- ing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged.
? 2003 microchip technology inc. ds39599c-page 251 pic18f2220/2320/4220/4320 23.5 program verification and code protection the overall structure of the code protection on the pic18 flash devices differs significantly from other picmicro ? devices. the user program memory is divided into five blocks. one of these is a boot block of 512 bytes. the remain- der of the memory is divided into four blocks on binary boundaries. each of the five blocks has three code protection bits associated with them. they are: code-protect bit (cpn) write-protect bit (wrtn) external block table read bit (ebtrn) figure 23-5 shows the program memory organization for 4 and 8-kbyte devices and the specific code protec- tion bit associated with each block. the actual locations of the bits are summarized in table 23-3. figure 23-5: code-protected prog ram memory for pic18f2x20/4x20 table 23-3: summary of code protection registers memory size/device block code protection controlled by: 4kbytes (pic18f2220/4220) 8kbytes (pic18f2320/4320) address range boot block boot block 000000h 0001ffh cpb, wrtb, ebtrb block 0 block 0 000200h 0007ffh cp0, wrt0, ebtr0 block 1 block 1 000800h 000fffh cp1, wrt1, ebtr1 unimplemented read ? 0 ?s block 2 001000h 0017ffh cp2, wrt2, ebtr2 unimplemented read ? 0 ?s block 3 001800h 001fffh cp3, wrt3, ebtr3 unimplemented read ? 0 ?s unimplemented read ? 0 ?s 002000h 1fffffh (unimplemented memory space) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 300008h config5l ? ? ? ? cp3 cp2 cp1 cp0 300009h config5h cpd cpb ? ? ? ? ? ? 30000ah config6l ? ? ? ? wrt3 wrt2 wrt1 wrt0 30000bh config6h wrtd wrtb wrtc ? ? ? ? ? 30000ch config7l ? ? ? ? ebtr3 ebtr2 ebtr1 ebtr0 30000dh config7h ? ebtrb ? ? ? ? ? ? legend: shaded cells are unimplemented.
pic18f2220/2320/4220/4320 ds39599c-page 252 ? 2003 microchip technology inc. 23.5.1 program memory code protection the program memory may be read to or written from any location using the table read and table write instructions. the device id may be read with table reads. the configuration registers may be read and written with the table read and table write instructions. in normal execution mode, the cpn bits have no direct effect. cpn bits inhibit external reads and writes. a block of user memory may be protected from table writes if the wrtn configuration bit is ? 0 ?. the ebtrn bits control table reads. for a block of user memory with the ebtrn bit set to ? 0 ?, a table read instruction that executes from within that block is allowed to read. a table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ? 0 ?s. figures 23-6 through 23-8 illustrate table write and table read protection. figure 23-6: table write (wrtn) disallowed note: code protection bits may only be written to a ? 0 ? from a ? 1 ? state. it is not possible to write a ? 1 ? to a bit in the ? 0 ? state. code pro- tection bits are only set to ? 1 ? by a full chip erase or block erase function. the full chip erase and block erase functions can only be initiated via icsp or an external programmer. 000000h 0001ffh 000200h 0007ffh 000800h 000fffh 001000h 0017ffh 001800h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 01 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblwt * tblptr = 0002ffh pc = 0007feh tblwt * pc = 0017feh register values program memory configuration bit settings results: all table writes disabled to blockn whenever wrtn = 0 .
? 2003 microchip technology inc. ds39599c-page 253 pic18f2220/2320/4220/4320 figure 23-7: external block t able read (ebtrn) disallowed figure 23-8: external block table read (ebtrn) allowed 000000h 0001ffh 000200h 0007ffh 000800h 000fffh 001000h 0017ffh 001800h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd * tblptr = 0002ffh pc = 000ffeh results: all table reads from external blocks to blockn are disabled whenever ebtrn = 0 . tablat register returns a value of ? 0 ?. register values program memory configuration bit settings 000000h 0001ffh 000200h 0007ffh 000800h 000fffh 001000h 0017ffh 001800h 001fffh wrtb, ebtrb = 11 wrt0, ebtr0 = 10 wrt1, ebtr1 = 11 wrt2, ebtr2 = 11 wrt3, ebtr3 = 11 tblrd * tblptr = 0002ffh pc = 0007feh register values program memory configuration bit settings results: table reads permitted within blockn, even when ebtrbn = 0 . tablat register returns the value of the data at the location tblptr.
pic18f2220/2320/4220/4320 ds39599c-page 254 ? 2003 microchip technology inc. 23.5.2 data eeprom code protection the entire data eeprom is protected from external reads and writes by two bits: cpd and wrtd. cpd inhibits external reads and writes of data eeprom. wrtd inhibits external writes to data eeprom. the cpu can continue to read and write data eeprom regardless of the protection bit settings. 23.5.3 configuration register protection the configuration registers can be write-protected. the wrtc bit controls protection of the configuration registers. in normal execution mode, the wrtc bit is readable only. wrtc can only be written via icsp or an external programmer. 23.6 id locations eight memory locations (200000h-200007h) are desig- nated as id locations, where the user can store check- sum or other code identification numbers. these locations are both readable and writable during normal execution through the tblrd and tblwt instructions, or during program/verify. the id locations can be read when the device is code-protected. 23.7 in-circuit serial programming pic18f2x20/4x20 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed (see table 23-5). 23.8 in-circuit debugger when the debug bit in configuration register, config4l, is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 23-4 shows which resources are required by the background debugger. table 23-4: debugger resources to use the in-circuit debugger function of the micro- controller, the design must implement in-circuit serial programming connections to mclr /v pp , v dd , v ss , rb7 and rb6. this will interface to the in-circuit debugger module available from microchip or one of the third party development tool companies. 23.9 low-voltage icsp programming the lvp bit in configuration register 4l (config4l<2>) enables low-voltage icsp program- ming (lvp). when lvp is enabled, the microcontroller can be programmed without requiring high voltage being applied to the mclr /v pp pin, but the rb5/pgm pin is then dedicated to controlling program mode entry and is not available as a general purpose i/o pin. lvp is enabled in erased devices. while programming using lvp, v dd is applied to the mclr /v pp pin as in normal execution mode. to enter programming mode, v dd is applied to the pgm pin. if low-voltage icsp programming mode will not be used, the lvp bit can be cleared and rb5/pgm becomes available as the digital i/o pin, rb5. the lvp bit may be set or cleared only when using standard high-voltage programming (v ihh applied to the mclr / v pp pin). once lvp has been disabled, only the stan- dard high-voltage programming is available and must be used to program the device. memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified v dd . if code-protected memory is to be erased, a block erase is required. if a block erase is to be performed when using low-voltage programming, the device must be supplied with v dd of 4.5v to 5.5v. table 23-5: icsp/icd connections i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes note 1: high-voltage programming is always available, regardless of the state of the lvp bit or the pgm pin, by applying v ihh to the mclr pin. 2: when low-voltage programming is enabled, the rb5 pin can no longer be used as a general purpose i/o pin. 3: when lvp is enabled, externally pull the pgm pin to v ss to allow normal program execution. signal pin notes pgd rb7 may require isolation from application circuits pgc rb6 mclr mclr v dd v dd v ss v ss pgm rb5 pull rb5 low if lvp is enabled
? 2003 microchip technology inc. ds39599c-page 255 pic18f2220/2320/4220/4320 24.0 instruction set summary the pic18 instruction set adds many enhancements to the previous picmicro instruction sets, while maintain- ing an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits) but there are three instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the oper- ation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: byte-oriented operations bit-oriented operations literal operations control operations the pic18 instruction set summary in table 24-2 lists byte-oriented , bit-oriented , literal and control opera- tions. table 24-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file register is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register desig- nator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: a literal value to be loaded into a file register (specified by ?k?) the desired fsr register to load the literal value into (specified by ?f?) no operand required (specified by ???) the control instructions may use some of the following operands: a program memory address (specified by ?n?) the mode of the call or return instructions (specified by ?s?) the mode of the table read and table write instructions (specified by ?m?) no operand required (specified by ???) all instructions are a single word except for three dou- ble word instructions. these three instructions were made double word instructions so that all the required information is available in these 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 24-1 shows the general formats that the instructions can have. all examples use the format ? nnh ? to represent a hexa- decimal number, where ? h ? signifies a hexadecimal digit. the instruction set summary, shown in table 24-2, lists the instructions recognized by the microchip assembler (mpasm tm ). section 24.2 ?instruction set? provides a description of each instruction. 24.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified and the result is stored according to either the instruction or the destination designator ?d?. a read operation is per- formed on a register even if the instruction writes to that register. for example, a ? bcf portb,1 ? instruction will read portb, clear bit 1 of the data, then write the result back to portb. the read operation would have the unintended result that any condition that sets the rbif flag would be cleared. the r-m-w operation may also copy the level of an input pin to its corresponding output latch.
pic18f2220/2320/4220/4320 ds39599c-page 256 ? 2003 microchip technology inc. table 24-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file register f dest destination either the wreg register or the specified register file location. f 8-bit register file address (0x00 to 0xff). fs 12-bit register file address (0x000 to 0xfff). this is the source address. fd 12-bit register file address (0x000 to 0xfff). this is the destination address. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes). *+ post-increment register (such as tblptr with table reads and writes). *- post-decrement register (such as tblptr with table reads and writes). +* pre-increment register (such as tb lptr with table reads and writes). n the relative address (2?s complement number) for relative branch instructions, or the direct address for call/branch and return instructions. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) u unused or unchanged. wreg working register (accumulator). x don't care (? 0 ? or ? 1 ?) . the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. tos top-of-stack. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. gie global interrupt enable bit. wdt watchdog timer. to time-out bit. pd power-down bit. c, dc, z, ov, n alu status bits carry, digit carry, zero, overflow, negative. [ ] optional. ( ) contents. assigned to. < > register bit field. in the set of. italics user defined term (font is courier).
? 2003 microchip technology inc. ds39599c-page 257 pic18f2220/2320/4220/4320 figure 24-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations 15 8 7 0 opcode k (literal) k = 8-bit immediate value byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 0x7f goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s
pic18f2220/2320/4220/4320 ds39599c-page 258 ? 2003 microchip technology inc. table 24-2: pic18fxxx instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 bit-oriented file register operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, d, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 2003 microchip technology inc. ds39599c-page 259 pic18f2220/2320/4220/4320 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation (note 4) pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c, dc none none none none none none all gie/gieh, peie/giel none none to , pd table 24-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
pic18f2220/2320/4220/4320 ds39599c-page 260 ? 2003 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsrx 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 (5) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 24-2: pic18fxxx instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are 2-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. 5: if the table write starts the write cycle to internal memory, the write will continue until terminated.
? 2003 microchip technology inc. ds39599c-page 261 pic18f2220/2320/4220/4320 24.2 instruction set addlw add literal to w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w to f syntax: [ label ] addwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr is used. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : addwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w=0xd9 reg = 0xc2
pic18f2220/2320/4220/4320 ds39599c-page 262 ? 2003 microchip technology inc. addwfc add w and carry bit to f syntax: [ label ] addwfc f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n, ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory loca- tion ?f?. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : addwfc reg, w before instruction carry bit = 1 reg = 0x02 w = 0x4d after instruction carry bit = 0 reg = 0x02 w = 0x50 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : andlw 0x5f before instruction w=0xa3 after instruction w = 0x03
? 2003 microchip technology inc. ds39599c-page 263 pic18f2220/2320/4220/4320 andwf and w with f syntax: [ label ] andwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : andwf reg, w before instruction w = 0x17 reg = 0xc2 after instruction w = 0x02 reg = 0xc2 bc branch if carry syntax: [ label ] bc n operands: -128 n 127 operation: if carry bit is ?1? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bc jump before instruction pc = address (here) after instruction if carry = 1; pc = address (jump) if carry = 0; pc = address (here+2)
pic18f2220/2320/4220/4320 ds39599c-page 264 ? 2003 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bn branch if negative syntax: [ label ] bn n operands: -128 n 127 operation: if negative bit is ?1? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here+2)
? 2003 microchip technology inc. ds39599c-page 265 pic18f2220/2320/4220/4320 bnc branch if not carry syntax: [ label ] bnc n operands: -128 n 127 operation: if carry bit is ?0? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here+2) bnn branch if not negative syntax: [ label ] bnn n operands: -128 n 127 operation: if negative bit is ?0? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here+2)
pic18f2220/2320/4220/4320 ds39599c-page 266 ? 2003 microchip technology inc. bnov branch if not overflow syntax: [ label ] bnov n operands: -128 n 127 operation: if overflow bit is ?0? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here+2) bnz branch if not zero syntax: [ label ] bnz n operands: -128 n 127 operation: if zero bit is ?0? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here+2)
? 2003 microchip technology inc. ds39599c-page 267 pic18f2220/2320/4220/4320 bra unconditional branch syntax: [ label ] bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example : here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: [ label ] bsf f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a
pic18f2220/2320/4220/4320 ds39599c-page 268 ? 2003 microchip technology inc. btfsc bit test file, skip if clear syntax: [ label ] btfsc f,b[,a] operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded and a nop is executed instead, mak- ing this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfsc : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: [ label ] btfss f,b[,a] operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution is discarded and a nop is executed instead, mak- ing this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here false true btfss : : flag, 1 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true)
? 2003 microchip technology inc. ds39599c-page 269 pic18f2220/2320/4220/4320 btg bit toggle f syntax: [ label ] btg f,b[,a] operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : btg portc, 4 before instruction: portc = 0111 0101 [0x75] after instruction: portc = 0110 0101 [0x65] bov branch if overflow syntax: [ label ] bov n operands: -128 n 127 operation: if overflow bit is ?1? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here+2)
pic18f2220/2320/4220/4320 ds39599c-page 270 ? 2003 microchip technology inc. bz branch if zero syntax: [ label ] bz n operands: -128 n 127 operation: if zero bit is ?1? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example : here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here+2) call subroutine call syntax: [ label ] call k [,s] operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2 mbyte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow regis- ters, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : here call there,fast before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss= status
? 2003 microchip technology inc. ds39599c-page 271 pic18f2220/2320/4220/4320 clrf clear f syntax: [ label ] clrf f [,a] operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits to and pd are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example : clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt postscaler = 0 to =1 pd =1
pic18f2220/2320/4220/4320 ds39599c-page 272 ? 2003 microchip technology inc. comf complement f syntax: [ label ] comf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : comf reg, w before instruction reg = 0x13 after instruction reg = 0x13 w=0xec (f ) cpfseq compare f with w, skip if f = w syntax: [ label ] cpfseq f [,a] operands: 0 f 255 a [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruc- tion is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfseq reg nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal)
? 2003 microchip technology inc. ds39599c-page 273 pic18f2220/2320/4220/4320 cpfsgt compare f with w, skip if f > w syntax: [ label ] cpfsgt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location 'f' to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfsgt reg ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: [ label ] cpfslt f [,a] operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected. if ?a? is ? 1 ?, the bsr will not be overridden (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here cpfslt reg nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless)
pic18f2220/2320/4220/4320 ds39599c-page 274 ? 2003 microchip technology inc. daw decimal adjust w register syntax: [ label ] daw operands: none operation: if [w<3:0> >9] or [dc = 1] then (w<3:0>) + 6 w<3:0>; else ( w<3:0>) w<3:0>; if [w<7:4> >9] or [c = 1] then ( w<7:4>) + 6 w<7:4>; else (w<7:4>) w<7:4>; status affected: c, dc encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addi- tion of two variables (each in packed bcd format) and produces a correct packed bcd result. the carry bit may be set by daw regard- less of its setting prior to the daw execution. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example1 : daw before instruction w=0xa5 c=0 dc = 0 after instruction w = 0x05 c=1 dc = 0 example 2 : before instruction w=0xce c=0 dc = 0 after instruction w = 0x34 c=1 dc = 0 decf decrement f syntax: [ label ] decf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : decf cnt, before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1
? 2003 microchip technology inc. ds39599c-page 275 pic18f2220/2320/4220/4320 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruc- tion which is already fetched is dis- carded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here decfsz cnt goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here+2) dcfsnz decrement f, skip if not 0 syntax: [ label ] dcfsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here dcfsnz temp zero : nzero : before instruction temp = ? after instruction temp = temp - 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero)
pic18f2220/2320/4220/4320 ds39599c-page 276 ? 2003 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example : goto there after instruction pc = address (there) incf increment f syntax: [ label ] incf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : incf cnt, before instruction cnt = 0xff z=0 c=? dc = ? after instruction cnt = 0x00 z=1 c=1 dc = 1
? 2003 microchip technology inc. ds39599c-page 277 pic18f2220/2320/4220/4320 incfsz increment f, skip if 0 syntax: [ label ] incfsz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here incfsz cnt nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: [ label ] infsnz f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here infsnz reg zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero)
pic18f2220/2320/4220/4320 ds39599c-page 278 ? 2003 microchip technology inc. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are or?ed with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : iorlw 0x35 before instruction w = 0x9a after instruction w=0xbf iorwf inclusive or w with f syntax: [ label ] iorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : iorwf result, w before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93
? 2003 microchip technology inc. ds39599c-page 279 pic18f2220/2320/4220/4320 lfsr load fsr syntax: [ label ] lfsr f,k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example : lfsr 2, 0x3ab after instruction fsr2h = 0x03 fsr2l = 0xab movf move f syntax: [ label ] movf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be any- where in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example : movf reg, w before instruction reg = 0x22 w=0xff after instruction reg = 0x22 w = 0x22
pic18f2220/2320/4220/4320 ds39599c-page 280 ? 2003 microchip technology inc. movff move f to f syntax: [ label ] movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff fff f s fff f d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register. the movff instruction should not be used to modify interrupt settings while any interrupt is enabled (see page 87). words: 2 cycles: 2 (3) q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example : movff reg1, reg2 before instruction reg1 = 0x33 reg2 = 0x11 after instruction reg1 = 0x33, reg2 = 0x33 movlb move literal to low nibble in bsr syntax: [ label ] movlb k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the 8-bit literal ?k? is loaded into the bank select register (bsr). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example : movlb 5 before instruction bsr register = 0x02 after instruction bsr register = 0x05
? 2003 microchip technology inc. ds39599c-page 281 pic18f2220/2320/4220/4320 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f [,a] operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : movwf reg before instruction w = 0x4f reg = 0xff after instruction w = 0x4f reg = 0x4f
pic18f2220/2320/4220/4320 ds39599c-page 282 ? 2003 microchip technology inc. mullw multiply literal with w syntax: [ label ] mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example : mullw 0xc4 before instruction w=0xe2 prodh = ? prodl = ? after instruction w=0xe2 prodh = 0xad prodl = 0x08 mulwf multiply w with f syntax: [ label ] mulwf f [,a] operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this opera- tion. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a?= 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example : mulwf reg before instruction w=0xc4 reg = 0xb5 prodh = ? prodl = ? after instruction w=0xc4 reg = 0xb5 prodh = 0x8a prodl = 0x94
? 2003 microchip technology inc. ds39599c-page 283 pic18f2220/2320/4220/4320 negf negate f syntax: [ label ] negf f [,a] operands: 0 f 255 a [0,1] operation: ( f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : negf reg, 1 before instruction reg = 0011 1010 [0x3a] after instruction reg = 1100 0110 [0xc6] nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example : none.
pic18f2220/2320/4220/4320 ds39599c-page 284 ? 2003 microchip technology inc. pop pop top of return stack syntax: [ label ] pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previ- ous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example : pop goto new before instruction tos = 0x0031a2 stack (1 level down) = 0x014332 after instruction tos = 0x014332 pc = new push push top of return stack syntax: [ label ] push operands: none operation: (pc+2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc+2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows to implement a software stack by modifying tos, and then push it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc+2 onto return stack no operation no operation example : push before instruction tos = 0x00345a pc = 0x000124 after instruction pc = 0x000126 tos = 0x000126 stack (1 level down) = 0x00345a
? 2003 microchip technology inc. ds39599c-page 285 pic18f2220/2320/4220/4320 rcall relative call syntax: [ label ] rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc+2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc+2+2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example : here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here+2) reset reset syntax: [ label ] reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example : reset after instruction registers = reset value flags* = reset value
pic18f2220/2320/4220/4320 ds39599c-page 286 ? 2003 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie [s] operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged. status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example : retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: [ label ] retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example : call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 0x07 after instruction w = value of kn
? 2003 microchip technology inc. ds39599c-page 287 pic18f2220/2320/4220/4320 return return from subroutine syntax: [ label ] return [s] operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their cor- responding registers, w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example : return after interrupt pc = tos rlcf rotate left f through carry syntax: [ label ] rlcf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) c, (c) dest<0> status affected: c, n, z encoding: 0011 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? = 1 , then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : rlcf reg, w before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 1100 1100 c= 1 c register f
pic18f2220/2320/4220/4320 ds39599c-page 288 ? 2003 microchip technology inc. rlncf rotate left f (no carry) syntax: [ label ] rlncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<7>) dest<0> status affected: n, z encoding: 0100 01da ffff ffff description: the contents of register ?f? are rotated one bit to the left. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : rlncf reg before instruction reg = 1010 1011 after instruction reg = 0101 0111 register f rrcf rotate right f through carry syntax: [ label ] rrcf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) c, (c) dest<7> status affected: c, n, z encoding: 0011 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : rrcf reg, w before instruction reg = 1110 0110 c= 0 after instruction reg = 1110 0110 w = 0111 0011 c= 0 c register f
? 2003 microchip technology inc. ds39599c-page 289 pic18f2220/2320/4220/4320 rrncf rotate right f (no carry) syntax: [ label ] rrncf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) dest, (f<0>) dest<7> status affected: n, z encoding: 0100 00da ffff ffff description: the contents of register ?f? are rotated one bit to the right. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in reg- ister ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : rrncf reg, 1, 0 before instruction reg = 1101 0111 after instruction reg = 1110 1011 example 2 : rrncf reg, w before instruction w=? reg = 1101 0111 after instruction w = 1110 1011 reg = 1101 0111 register f setf set f syntax: [ label ] setf f [,a] operands: 0 f 255 a [0,1] operation: ffh f status affected: none encoding: 0110 100a ffff ffff description: the contents of the specified regis- ter are set to ffh. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example : setf reg before instruction reg = 0x5a after instruction reg = 0xff
pic18f2220/2320/4220/4320 ds39599c-page 290 ? 2003 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example : sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: [ label ] subfwb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?d? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subfwb reg before instruction reg = 0x03 w = 0x02 c = 0x01 after instruction reg = 0xff w = 0x02 c = 0x00 z = 0x00 n = 0x01 ; result is negative example 2 : subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3 : subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0
? 2003 microchip technology inc. ds39599c-page 291 pic18f2220/2320/4220/4320 sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 0x02 before instruction w=1 c=? after instruction w=1 c = 1 ; result is positive z=0 n=0 example 2 : sublw 0x02 before instruction w=2 c=? after instruction w=0 c = 1 ; result is zero z=1 n=0 example 3 : sublw 0x02 before instruction w=3 c=? after instruction w = ff ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: [ label ] subwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if = ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subwf reg before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2 : subwf reg, w before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3 : subwf reg before instruction reg = 0x01 w = 0x02 c=? after instruction reg = 0xffh ;(2?s complement) w = 0x02 c = 0x00 ; result is negative z = 0x00 n = 0x01
pic18f2220/2320/4220/4320 ds39599c-page 292 ? 2003 microchip technology inc. subwfb subtract w from f with borrow syntax: [ label ] subwfb f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (bor- row) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1 : subwfb reg, 1, 0 before instruction reg = 0x19 (0001 1001) w = 0x0d (0000 1101) c = 0x01 after instruction reg = 0x0c (0000 1011) w = 0x0d (0000 1101) c = 0x01 z = 0x00 n = 0x00 ; result is positive example 2 : subwfb reg, 0, 0 before instruction reg = 0x1b (0001 1011) w = 0x1a (0001 1010) c = 0x00 after instruction reg = 0x1b (0001 1011) w = 0x00 c = 0x01 z = 0x01 ; result is zero n = 0x00 example 3: subwfb reg, 1, 0 before instruction reg = 0x03 (0000 0011) w = 0x0e (0000 1101) c = 0x01 after instruction reg = 0xf5 (1111 0100) ; [2?s comp] w = 0x0e (0000 1101) c = 0x00 z = 0x00 n = 0x01 ; result is negative
? 2003 microchip technology inc. ds39599c-page 293 pic18f2220/2320/4220/4320 swapf swap f syntax: [ label ] swapf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of reg- ister ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : swapf reg before instruction reg = 0x53 after instruction reg = 0x35
pic18f2220/2320/4220/4320 ds39599c-page 294 ? 2003 microchip technology inc. tblrd table read syntax: [ label ] tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr - no change; if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) +1 tblptr; if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) -1 tblptr; if tblrd +*, (tblptr) +1 tblptr; (prog mem (tblptr)) tablat; status affected:none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (cont?d) example1 : tblrd *+ ; before instruction tablat = 0x55 tblptr = 0x00a356 memory(0x00a356) = 0x34 after instruction tablat = 0x34 tblptr = 0x00a357 example2 : tblrd +* ; before instruction tablat = 0xaa tblptr = 0x01a357 memory(0x01a357) = 0x12 memory(0x01a358) = 0x34 after instruction tablat = 0x34 tblptr = 0x01a358
? 2003 microchip technology inc. ds39599c-page 295 pic18f2220/2320/4220/4320 tblwt table write syntax: [ label ] tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr - no change; if tblwt*+, (tablat) holding register; (tblptr) +1 tblptr; if tblwt*-, (tablat) holding register; (tblptr) -1 tblptr; if tblwt+*, (tblptr) +1 tblptr; (tablat) holding register; status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 6.0 ?flash program memory? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2 mbtye address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 :most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: no change post-increment post-decrement pre-increment tblwt table write (continued) words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register ) example1 : tblwt *+; before instruction tablat = 0x55 tblptr = 0x00a356 holding register (0x00a356) = 0xff after instructions (table write completion) tablat = 0x55 tblptr = 0x00a357 holding register (0x00a356) = 0x55 example 2 : tblwt +*; before instruction tablat = 0x34 tblptr = 0x01389a holding register (0x01389a) = 0xff holding register (0x01389b) = 0xff after instruction (table write completion) tablat = 0x34 tblptr = 0x01389b holding register (0x01389a) = 0xff holding register (0x01389b) = 0x34
pic18f2220/2320/4220/4320 ds39599c-page 296 ? 2003 microchip technology inc. tstfsz test f, skip if 0 syntax: [ label ] tstfsz f [,a] operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction, fetched during the current instruc- tion execution is discarded and a nop is executed, making this a two- cycle instruction. if ?a? is ? 0 ?, the access bank will be selected, over- riding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example : here tstfsz cnt nzero : zero : before instruction pc = address (here) after instruction if cnt = 0x00, pc = address (zero) if cnt 0x00, pc = address (nzero) xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xor?ed with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example : xorlw 0xaf before instruction w=0xb5 after instruction w = 0x1a
? 2003 microchip technology inc. ds39599c-page 297 pic18f2220/2320/4220/4320 xorwf exclusive or w with f syntax: [ label ] xorwf f [,d [,a]] operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank will be selected, overriding the bsr value. if ?a? is ? 1 ?, then the bank will be selected as per the bsr value (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example : xorwf reg before instruction reg = 0xaf w=0xb5 after instruction reg = 0x1a w=0xb5
pic18f2220/2320/4220/4320 ds39599c-page 298 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page299 pic18f2220/2320/4220/4320 25.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? - picdem msc -microid ? -can - powersmart ? -analog 25.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - absolute listing file (mixed assembly and c) - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 25.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
pic18f2220/2320/4220/4320 ds39599c-page 300 ? 2003 microchip technology inc. 25.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 25.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command- line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 25.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 25.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 25.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2003 microchip technology inc. ds39599c-page301 pic18f2220/2320/4220/4320 25.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 25.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab inte- grated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 25.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 25.13 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant.
pic18f2220/2320/4220/4320 ds39599c-page 302 ? 2003 microchip technology inc. 25.14 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 25.15 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 25.16 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 25.17 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 25.18 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 fam- ily of microcontrollers. picdem 4 is intended to show- case the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. included on the demo board are provisions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for program- ming via icsp and development with mplab icd 2, 2x16 liquid crystal display, pcb footprints for h-bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a prototyping area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide. 25.19 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion.
? 2003 microchip technology inc. ds39599c-page303 pic18f2220/2320/4220/4320 25.20 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 25.21 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 25.22 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user's guide (on cd rom), pickit 1 tutorial software and code for vari- ous applications. also included are mplab ? ide (inte- grated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 25.23 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 25.24 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product line card for the complete list of demonstration and evaluation kits.
pic18f2220/2320/4220/4320 ds39599c-page 304 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 305 pic18f2220/2320/4220/4320 26.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-55c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd , mclr and ra4) .......................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v voltage on ra4 with respect to v ss ............................................................................................................... 0v to +8.5v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v o l x i ol ) 2: voltage spikes below v ss at the mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr /v pp pin, rather than pulling this pin directly to v ss . ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic18f2220/2320/4220/4320 ds39599c-page 306 ? 2003 microchip technology inc. figure 26-1: pic18f2220/2320/4220/4320 voltage-frequency graph (industrial) figure 26-2: pic18f2220/2320/4220/4320 voltage-frequency graph (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18f2x20/4x20 4.2v frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 25 mhz 5.0v 3.5v 3.0v 2.5v pic18f2x20/4x20 4.2v
? 2003 microchip technology inc. ds39599c-page 307 pic18f2220/2320/4220/4320 figure 26-3: pic18lf2220/2320/4220/4320 voltage-frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 40 mhz 5.0v 3.5v 3.0v 2.5v pic18lf2x20/4x20 f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz note: v ddappmin is the minimum voltage of the picmicro ? device in the application. 4 mhz 4.2v
pic18f2220/2320/4220/4320 ds39599c-page 308 ? 2003 microchip technology inc. 26.1 dc characteristics: supply voltage pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ max units conditions v dd supply voltage d001 pic18lf2x20/4x20 2.0 ? 5.5 v hs, xt, rc and lp osc mode pic18f2x20/4x20 4.2 ? 5.5 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd start voltage to ensure internal power-on reset signal ? ? 0.7 v see section on power-on reset for details d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section on power-on reset for details v bor brown-out reset voltage pic18lf2x20/4x20 industrial low voltage d005 borv1:borv0 = 11 na ? na v reserved borv1:borv0 = 10 2.50 2.72 2.94 v borv1:borv0 = 01 3.88 4.22 4.56 v borv1:borv0 = 00 4.18 4.54 4.90 v d005 pic18f2x20/4x20 industrial borv1:borv0 = 1x na ? na v not in operating voltage range of device borv1:borv0 = 01 3.88 4.22 4.56 v borv1:borv0 = 00 4.18 4.54 4.90 v d005e pic18f2x20/4x20 extended borv1:borv0 = 1x na ? na v not in operating voltage range of device borv1:borv0 = 01 3.71 4.22 4.73 v borv1:borv0 = 00 4.00 4.54 5.08 v legend: shading of rows is to assist in readability of the table. note 1: this is the limit to which v dd can be lowered in sleep mode, or duri ng a device reset, without losing ram data.
? 2003 microchip technology inc. ds39599c-page 309 pic18f2220/2320/4220/4320 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions power-down current (i pd ) (1) pic18lf2x20/4x20 0.1 0.5 a -40c v dd = 2.0v, ( sleep mode) 0.1 0.5 a +25c 0.2 1.7 a +85c pic18lf2x20/4x20 0.1 0.5 a -40c v dd = 3.0v, ( sleep mode) 0.1 0.5 a +25c 0.3 1.7 a +85c all devices 0.1 2.0 a -40c v dd = 5.0v, ( sleep mode) 0.1 2.0 a +25c 0.4 6.5 a +85c extended devices 11.2 50 a +125c supply current (i dd ) (2,3) pic18lf2x20/4x20 11 25 a -40c v dd = 2.0v f osc = 31 khz ( rc_run mode, internal oscillator source) 13 25 a+25c 14 25 a+85c pic18lf2x20/4x20 34 40 a -40c v dd = 3.0v 28 40 a+25c 25 40 a+85c all devices 77 80 a -40c v dd = 5.0v 62 80 a+25c 53 80 a+85c extended devices 50 80 a +125c legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f2220/2320/4220/4320 ds39599c-page 310 ? 2003 microchip technology inc. supply current (i dd ) (2,3) pic18lf2x20/4x20 100 220 a -40c v dd = 2.0v f osc = 1 mhz ( rc_run mode, internal oscillator source) 110 220 a+25c 120 220 a+85c pic18lf2x20/4x20 180 330 a -40c v dd = 3.0v 180 330 a+25c 170 330 a+85c all devices 340 550 a -40c v dd = 5.0v 330 550 a+25c 310 550 a+85c extended devices 410 650 a +125c pic18lf2x20/4x20 350 600 a -40c v dd = 2.0v f osc = 4 mhz ( rc_run mode, internal oscillator source) 360 600 a+25c 370 600 a+85c pic18lf2x20/4x20 580 900 a -40c v dd = 3.0v 580 900 a+25c 560 900 a+85c all devices 1.1 1.8 ma -40c v dd = 5.0v 1.1 1.8 ma +25c 1.0 1.8 ma +85c extended devices 1.2 1.8 ma +125c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2003 microchip technology inc. ds39599c-page 311 pic18f2220/2320/4220/4320 supply current (i dd ) (2,3) pic18lf2x20/4x20 4.7 8 a -40c v dd = 2.0v f osc = 31 khz ( rc_idle mode, internal oscillator source) 4.6 8 a+25c 5.1 11 a+85c pic18lf2x20/4x20 6.9 11 a -40c v dd = 3.0v 6.3 11 a+25c 6.8 15 a+85c all devices 12 16 a -40c v dd = 5.0v 10 16 a+25c 10 22 a+85c extended devices 25 75 a +125c pic18lf2x20/4x20 49 150 a -40c v dd = 2.0v f osc = 1 mhz ( rc_idle mode, internal oscillator source) 52 150 a+25c 56 150 a+85c pic18lf2x20/4x20 73 180 a -40c v dd = 3.0v 77 180 a+25c 77 180 a+85c all devices 130 300 a -40c v dd = 5.0v 130 300 a+25c 130 300 a+85c extended devices 350 435 a +125c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f2220/2320/4220/4320 ds39599c-page 312 ? 2003 microchip technology inc. supply current (i dd ) (2,3) pic18lf2x20/4x20 140 275 a -40c v dd = 2.0v f osc = 4 mhz ( rc_idle mode, internal oscillator source) 140 275 a+25c 150 275 a+85c pic18lf2x20/4x20 220 375 a -40c v dd = 3.0v 220 375 a+25c 210 375 a+85c all devices 390 800 a -40c v dd = 5.0v 400 800 a+25c 380 800 a+85c extended devices 410 800 a +125c pic18lf2x20/4x20 150 250 a -40c v dd = 2.0v f osc = 1 mh z ( pri_run , ec oscillator) 150 250 a+25c 160 250 a+85c pic18lf2x20/4x20 340 350 a -40c v dd = 3.0v 300 350 a+25c 280 350 a+85c all devices 0.72 1.0 ma -40c v dd = 5.0v 0.63 1.0 ma +25c 0.57 1.0 ma +85c extended devices 0.53 1.0 ma +125c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2003 microchip technology inc. ds39599c-page 313 pic18f2220/2320/4220/4320 supply current (i dd ) (2,3) pic18lf2x20/4x20 440 600 a -40c v dd = 2.0v f osc = 4 mhz ( pri_run , ec oscillator) 450 600 a+25c 460 600 a+85c pic18lf2x20/4x20 0.80 1.0 ma -40c v dd = 3.0v 0.78 1.0 ma +25c 0.77 1.0 ma +85c all devices 1.6 2.0 ma -40c v dd = 5.0v 1.5 2.0 ma +25c 1.5 2.0 ma +85c extended devices 1.5 2.0 ma +125c extended devices 6.3 9.0 ma +125c v dd = 4.2v f osc = 25 mh z ( pri_run , ec oscillator) 7.9 10.0 ma +125c v dd = 5.0v all devices 9.5 12 ma -40c v dd = 4.2v f osc = 40 mh z ( pri_run , ec oscillator) 9.7 12 ma +25c 9.9 12 ma +85c all devices 11.9 15 ma -40c v dd = 5.0v 12.1 15 ma +25c 12.3 15 ma +85c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f2220/2320/4220/4320 ds39599c-page 314 ? 2003 microchip technology inc. supply current (i dd ) (2,3) pic18lf2x20/4x20 37 50 a -40c v dd = 2.0v f osc = 1 mhz ( pri_idle mode, ec oscillator) 37 50 a+25c 38 60 a+85c pic18lf2x20/4x20 58 80 a -40c v dd = 3.0v 59 80 a+25c 60 100 a+85c all devices 110 180 a -40c v dd = 5.0v 110 180 a+25c 110 180 a+85c extended devices 125 300 a +125c pic18lf2x20/4x20 140 180 a -40c v dd = 2.0v f osc = 4 mhz ( pri_idle mode, ec oscillator) 140 180 a+25c 140 180 a+85c pic18lf2x20/4x20 220 280 a -40c v dd = 3.0v 230 280 a+25c 230 280 a+85c all devices 410 525 a -40c v dd = 5.0v 420 525 a+25c 430 525 a+85c extended devices 450 800 a +125c extended devices 2.2 3.0 ma +125c v dd = 4.2v f osc = 25 mh z ( pri_idle , ec oscillator) 2.7 3.5 ma +125c v dd = 5.0v 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2003 microchip technology inc. ds39599c-page 315 pic18f2220/2320/4220/4320 supply current (i dd ) (2,3) all devices 3.1 4.1 ma -40c v dd = 4.2 v f osc = 40 mhz ( pri_idle mode, ec oscillator) 3.2 4.1 ma +25c 3.3 4.1 ma +85c all devices 4.4 5.1 ma -40c v dd = 5.0v 4.6 5.1 ma +25c 4.6 5.1 ma +85c pic18lf2x20/4x20 9 15 a -40c v dd = 2.0v f osc = 32 khz (4) ( sec_run mode, timer1 as clock) 10 15 a+25c 13 18 a+85c pic18lf2x20/4x20 22 30 a -40c v dd = 3.0v 21 30 a+25c 20 35 a+85c all devices 50 80 a -40c v dd = 5.0v 50 80 a+25c 45 85 a+85c pic18lf2x20/4x20 5.1 9 a -40c v dd = 2.0v f osc = 32 khz (4) ( sec_idle mode, timer1 as clock) 5.8 9 a+25c 7.9 11 a+85c pic18lf2x20/4x20 7.9 12 a -40c v dd = 3.0v 8.9 12 a+25c 10.5 14 a+85c all devices 13 20 a -40c v dd = 5.0v 16 20 a+25c 18 25 a+85c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f2220/2320/4220/4320 ds39599c-page 316 ? 2003 microchip technology inc. module differential currents ( ? i wdt , ? i bor , ? i lvd , ? i oscb , ? i ad ) d022 ( ? i wdt ) watchdog timer 1.5 3.8 a -40c v dd = 2.0v 2.2 3.8 a+25c 2.7 4.0 a+85c 2.3 4.6 a -40c v dd = 3.0v 2.7 4.6 a+25c 3.1 4.8 a+85c 3.0 10.0 a -40c v dd = 5.0v 3.3 10.0 a+25c 3.9 10.0 a+85c extended devices only 4.0 13.0 a +125c d022a brown-out reset 17 35.0 a-40 c to +85 cv dd = 3.0v ( ? i bor ) 47 45.0 a-40 c to +85 c v dd = 5.0v extended devices only 48 50.0 a-40 c to +125 c d022b low-voltage detect 14 25.0 a-40 c to +85 c v dd = 2.0v ( ? i lvd ) 18 35.0 a-40 c to +85 cv dd = 3.0v 21 45.0 a-40 c to +85 c v dd = 5.0v extended devices only 24 50.0 a-40 c to +125 c 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
? 2003 microchip technology inc. ds39599c-page 317 pic18f2220/2320/4220/4320 d025 timer1 oscillator 2.1 2.2 a-40 c v dd = 2.0v 32 khz on timer1 (4) ( ? i oscb )1.82.2 a+25c 2.1 2.2 a+85c 2.2 3.8 a-40 c v dd = 3.0v 32 khz on timer1 (4) 2.6 3.8 a+25c 2.9 3.8 a+85c 3.0 6.0 a-40 c v dd = 5.0v 32 khz on timer1 (4) 3.2 6.0 a+25c 3.4 7.0 a+85c d026 ( ? i ad ) a/d converter 1.0 2.0 a-40 c to +85 c v dd = 2.0v a/d on, not converting 1.0 2.0 a-40 c to +85 c v dd = 3.0v 1.0 2.0 a-40 c to +85 c v dd = 5.0v extended devices only 1.0 8.0 a-40 c to +125 c v dd = 5.0v 26.2 dc characteristics: power-down and supply current pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device typ max units conditions legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be estimated by the formula ir = v dd /2r ext (ma) with r ext in k ? . 4: standard low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost.
pic18f2220/2320/4220/4320 ds39599c-page 318 ? 2003 microchip technology inc. 26.3 dc characteristics: pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd vv dd < 4.5v d030a ? 0.8 v 4.5v v dd 5.5v d031 with schmitt trigger buffer rc3 and rc4 v ss v ss 0.2 v dd 0.3 v dd v v d032 mclr v ss 0.2 v dd v d032a osc1 and t1osi v ss 0.2 v dd v lp, xt, hs, hspll modes (1) d033 osc1 v ss 0.2 v dd vec mode (1) v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd vv dd < 4.5v d040a 2.0 v dd v4.5v v dd 5.5v d041 with schmitt trigger buffer rc3 and rc4 0.8 v dd 0.7 v dd v dd v dd v v d042 mclr 0.8 v dd v dd v d042a osc1 and t1osi 1.6 v dd v lp, xt, hs, hspll modes (1) d043 osc1 0.8 v dd v dd vec mode (1) i il input leakage current (2,3) d060 i/o ports ? 0.2 av ss v pin v dd , pin at high-impedance d061 mclr , ra4 ? 1.0 avss v pin v dd d063 osc1 ? 1.0 avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 50 400 av dd = 5v, v pin = v ss note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
? 2003 microchip technology inc. ds39599c-page 319 pic18f2220/2320/4220/4320 v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, -40 c to +125 c d083 osc2/clko (rc mode) ?0.6vi ol = 1.6 ma, v dd = 4.5v, -40 c to +85 c d083a ? 0.6 v i ol = 1.2 ma, v dd = 4.5v, -40 c to +125 c v oh output high voltage (3) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd ? 0.7 ? v i oh = -2.5 ma, v dd = 4.5v, -40 c to +125 c d092 osc2/clko (rc mode) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 4.5v, -40 c to +85 c d092a v dd ? 0.7 ? v i oh = -1.0 ma, v dd = 4.5v, -40 c to +125 c d150 v od open-drain high voltage ? 8.5 v ra4 pin capacitive loading specs on output pins d100 (4) c osc2 osc2 pin ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in rc mode) ? 50 pf to meet the ac timing specifications d102 c b scl, sda ? 400 pf in i 2 c mode 26.3 dc characteristics: pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min max units conditions note 1: in rc oscillator configuration, the osc1/clki pin is a schmitt trigger input. it is not recommended that the picmicro device be driven with an external clock while in rc mode. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: parameter is characterized but not tested.
pic18f2220/2320/4220/4320 ds39599c-page 320 ? 2003 microchip technology inc. table 26-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions internal program memory programming specifications d110 v pp voltage on mclr /v pp pin 9.00 ? 13.25 v (note 2) d112 i pp current into mclr /v pp pin ? ? 300 a d113 i ddp supply current during programming ??1.0ma data eeprom memory d120 e d byte endurance 100k 10k 1m 100k ? ? e/w e/w -40 c to +85 c -40 c to +125 c d121 v drw v dd for read/write v min ? 5.5 v using eecon to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 4 ? ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/write cycles before refresh (1) 1m 100k 10m 1m ? ? e/w e/w -40c to +85c -40 c to +125 c program flash memory d130 e p cell endurance 10k 1k 100k 10k ? ? e/w e/w -40 c to +85 c -40 c to +125 c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v ie v dd for block erase 4.5 ? 5.5 v using icsp port d132a v iw v dd for externally timed erase or write 4.5 ? 5.5 v using icsp port d132b v pew v dd for self-timed write v min ?5.5vv min = minimum operating voltage d133 t ie icsp block erase cycle time ? 4 ? ms v dd > 4.5v d133a t iw icsp erase or write cycle time (externally timed) 1??msv dd > 4.5v d133a t iw self-timed write cycle time ? 2 ? ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: refer to section 7.8 ?using the data eeprom? for a more detailed discussion on data eeprom endurance. 2: required only if low-voltage programming is disabled.
? 2003 microchip technology inc. ds39599c-page 321 pic18f2220/2320/4220/4320 table 26-2: comparator specifications table 26-3: voltage reference specifications operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +125c, unless otherwise stated. param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 ? v dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 ? ? db 300 300a t resp response time (1)* ?150400 600 ns ns pic18fxx20 pic18lfxx20 301 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd . operating conditions: 3.0v < v dd < 5.5v, -40c < t a < +125c, unless otherwise stated. param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? ? ? 1/2 1/2 lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) d312 vr ur unit resistor value (r) * ?2k? ? 310 t set settling time (1)* ? ? 10 s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from ? 0000 ? to ? 1111 ?.
pic18f2220/2320/4220/4320 ds39599c-page 322 ? 2003 microchip technology inc. figure 26-4: low-voltage detect characteristics table 26-4: low-voltage detect characteristics pic18lf2220/2320/4220/4320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f2220/2320/4220/4320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. symbol characteristic min typ? max units conditions d420 lvd voltage on v dd transition high to low industrial pic18lf2x20/4x20 lvdl<3:0> = 0000 n/a n/a n/a v reserved lvdl<3:0> = 0001 n/a n/a n/a v reserved lvdl<3:0> = 0010 2.15 2.26 2.37 v lvdl<3:0> = 0011 2.33 2.45 2.58 v lvdl<3:0> = 0100 2.43 2.55 2.68 v lvdl<3:0> = 0101 2.63 2.77 2.91 v lvdl<3:0> = 0110 2.73 2.87 3.01 v lvdl<3:0> = 0111 2.91 3.07 3.22 v lvdl<3:0> = 1000 3.20 3.36 3.53 v lvdl<3:0> = 1001 3.39 3.57 3.75 v lvdl<3:0> = 1010 3.49 3.67 3.85 v lvdl<3:0> = 1011 3.68 3.87 4.07 v lvdl<3:0> = 1100 3.87 4.07 4.28 v lvdl<3:0> = 1101 4.06 4.28 4.49 v lvdl<3:0> = 1110 4.37 4.60 4.82 v d420 lvd voltage on v dd transition high to low industrial pic18f2x20/4x20 lvdl<3:0> = 1011 3.68 3.87 4.07 v lvdl<3:0> = 1100 3.87 4.07 4.28 v lvdl<3:0> = 1101 4.06 4.28 4.49 v lvdl<3:0> = 1110 4.37 4.60 4.82 v d420e lvd voltage on v dd transition high to low extended pic18f2x20/4x20 lvdl<3:0> = 1011 3.48 3.87 4.25 v lvdl<3:0> = 1100 3.66 4.07 4.48 v lvdl<3:0> = 1101 3.85 4.28 4.70 v lvdl<3:0> = 1110 4.14 4.60 5.05 v legend: shading of rows is to assist in readability of the table. ? production tested at t amb = 25c. specifications ov er temperature limits ens ured by characterization. v lvd lvdif v dd (lvdif set by hardware) (lvdif can be cleared in software)
? 2003 microchip technology inc. ds39599c-page 323 pic18f2220/2320/4220/4320 26.4 ac (timing) characteristics 26.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clko rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition
pic18f2220/2320/4220/4320 ds39599c-page 324 ? 2003 microchip technology inc. 26.4.2 timing conditions the temperature and voltages specified in table 26-5 apply to all timing specifications unless otherwise noted. figure 26-5 specifies the load conditions for the timing specifications. table 26-5: temperature and voltage specifications ? ac figure 26-5: load conditions for devi ce timing specifications note: because of space limitations, the generic terms ?pic18fxx20? and ?pic18lfxx20? are used throughout this section to refer to the pic18f2220/2320/4220/4320 and pic18lf2220/2320/4220/4320 families of devices specifically and only those devices. ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended operating voltage v dd range as described in dc spec section 26.1 and section 26.3 . lf parts operate up to industrial temperatures only. v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports load condition 1 load condition 2
? 2003 microchip technology inc. ds39599c-page 325 pic18f2220/2320/4220/4320 26.4.3 timing diagrams and specifications figure 26-6: external clock timing (all modes except pll) table 26-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 40 mhz ec, ecio (industrial) dc 25 mhz ec, ecio (extended) oscillator frequency (1) dc 4 mhz rc osc 0.1 1 mhz xt osc 4 25 mhz hs osc 4 10 mhz hs + pll osc (industrial) 4 6.25 mhz hs + pll osc (extended) 5 33 khz lp osc mode 1t osc external clki period (1) 25 ? ns ec, ecio (industrial) 40 ? ns ec, ecio (extended) oscillator period (1) 250 ? ns rc osc 1? sxt osc 40 100 250 250 ns ns hs osc hs + pll osc (industrial) 160 250 ns hs + pll osc (extended) 30 ? slp osc 2t cy instruction cycle time (1) 100 160 ? ? ns ns t cy = 4/f osc (industrial) t cy = 4/f osc (extended) 3t os l, t os h external clock in (osc1) high or low time 30 ? ns xt osc 2.5 ? slp osc 10 ? ns hs osc 4t os r, t os f external clock in (osc1) rise or fall time ? 20 ns xt osc ? 50 ns lp osc ? 7.5 ns hs osc note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices.
pic18f2220/2320/4220/4320 ds39599c-page 326 ? 2003 microchip technology inc. table 26-7: pll clock timing specifications (v dd = 4.2v to 5.5v) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 4 ? 10 mhz hs mode only f11 f sys on-chip vco system frequency 16 ? 40 mhz hs mode only f12 t pll pll start-up time (lock time) ? ? 2 ms f13 ? clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. table 26-8: internal rc accuracy: pic18f2220/2320/4220/4320 (industrial) pic18lf2220/2320/4220/4320 (industrial, extended ) pic18lf1220/1320 (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial pic18f1220/1320 (industrial, extended) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. device min typ max units conditions intosc accuracy @ freq = 8 mhz, 4 mhz, 2 mhz, 1 mhz, 500 khz, 250 khz, 125 khz (1) f14 pic18lf2220/2320/4220/4320 -2 +/-1 2 % +25c v dd = 2.7-3.3v f15 -5 ? 5 % -10c to +85c v dd = 2.7-3.3v f16 -10 ? 10 % -40c to +85c v dd = 2.7-3.3v f17 pic18f2220/2320/4220/4320 -2 +/-1 2 % +25c v dd = 4.5-5.5v f18 -5 ? 5 % -10c to +85c v dd = 4.5-5.5v f19 -10 ? 10 % -40c to +85c v dd = 4.5-5.5v intrc accuracy @ freq = 31 khz (2) f20 pic18lf2220/2320/4220/4320 26.562 ? 35.938 khz -40c to +85c v dd = 2.7-3.3v f21 pic18f2220/2320/4220/4320 26.562 ? 35.938 khz -40c to +85c v dd = 4.5-5.5v legend: shading of rows is to assist in readability of the table. note 1: frequency calibrated at 25c. osctune register can be used to compensate for temperature drift. 2: intrc frequency after calibration. 3: change of intrc frequency as v dd changes.
? 2003 microchip technology inc. ds39599c-page 327 pic18f2220/2320/4220/4320 figure 26-7: clko and i/o timing table 26-9: clko and i/o timing requirements note: refer to figure 26-5 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 to clko ? 75 200 ns (1) 11 t os h2 ck hosc1 to clko ? 75 200 ns (1) 12 t ck r clko rise time ? 35 100 ns (1) 13 t ck f clko fall time ? 35 100 ns (1) 14 t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns (1) 15 t io v2 ck h port in valid before clko 0.25 t cy + 25 ? ? ns (1) 16 t ck h2 io i port in hold after clko 0??ns (1) 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) pic18 f xx20 100 ? ? ns 18a pic18 lf xx20 200 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0 ? ? ns 20 t io r port output rise time pic18 f xx20 ? 10 25 ns 20a pic18 lf xx20 ? ? 60 ns 21 t io f port output fall time pic18 f xx20 ? 10 25 ns 21a pic18 lf xx20 ? ? 60 ns note 1: measurements are taken in rc mode, where clko output is 4 x t osc .
pic18f2220/2320/4220/4320 ds39599c-page 328 ? 2003 microchip technology inc. figure 26-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 26-9: brown-out reset timing table 26-10: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 t mc lmclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 3.48 4.00 4.71 ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 57.0 65.5 77.2 ms 34 tioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 35 t bor brown-out reset pulse width 200 ? ? sv dd b vdd (see d005) 36 t ivrst time for internal reference voltage to become stable ?2050 s 37 t lvd low-voltage detect pulse width 200 ? ? sv dd v lvd v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 26-5 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable
? 2003 microchip technology inc. ds39599c-page 329 pic18f2220/2320/4220/4320 figure 26-10: timer0 and timer1 external clock timings table 26-11: timer0 and timer1 external clock requirements note: refer to figure 26-5 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t1cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 t t 0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or t cy + 40 n ?nsn = prescale value (1, 2, 4,..., 256) 45 t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler pic18 f xx20 10 ? ns pic18 lf xx20 25 ? ns asynchronous pic18 f xx20 30 ? ns pic18 lf xx20 50 ? ns 46 t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler pic18 f xx20 10 ? ns pic18 lf xx20 25 ? ns asynchronous pic18 f xx20 30 ? ns pic18 lf xx20 50 ? ns 47 t t 1p t1cki input period synchronous greater of: 20 ns or t cy + 40 n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns f t 1 t1cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t1cki clock edge to timer increment 2 t osc 7 t osc ?
pic18f2220/2320/4220/4320 ds39599c-page 330 ? 2003 microchip technology inc. figure 26-11: capture/compare/pwm timings (all ccp modules) table 26-12: capture/compare/pwm requirements (all ccp modules) note: refer to figure 26-5 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xx20 10 ? ns pic18 lf xx20 20 ? ns 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler pic18 f xx20 10 ? ns pic18 lf xx20 20 ? ns 52 t cc p ccpx input period 3 t cy + 40 n ?nsn = prescale value (1,4 or 16) 53 t cc r ccpx output fall time pic18 f xx20 ? 25 ns pic18 lf xx20 ? 45 ns 54 t cc f ccpx output fall time pic18 f xx20 ? 25 ns pic18 lf xx20 ? 45 ns
? 2003 microchip technology inc. ds39599c-page 331 pic18f2220/2320/4220/4320 figure 26-12: parallel slave port timing (pic18f4x20) table 26-13: parallel slave port requirements (pic18f4x20) note: refer to figure 26-5 for load conditions. re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65 param. no. symbol characteristic min max units conditions 62 t dt v2 wr h data in valid before wr or cs (setup time) 20 ? ns 63 t wr h2 dt iwr or cs to data?in invalid (hold time) pic18 f xx20 20 ? ns pic18 lf xx20 35 ? ns 64 t rd l2 dt vrd and cs to data?out valid ? 80 ns 65 t rd h2 dt ird or cs to data?out invalid 10 30 ns 66 t ibf inh inhibit of the ibf flag bit being cleared from wr or cs ?3 t cy
pic18f2220/2320/4220/4320 ds39599c-page 332 ? 2003 microchip technology inc. figure 26-13: example spi ma ster mode timing (cke = 0 ) table 26-14: example spi mode requirements (master mode, cke = 0 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 26-5 for load conditions. param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xx20 ? 25 ns pic18 lf xx20 ? 45 ns 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) pic18 f xx20 ? 25 ns pic18 lf xx20 ? 45 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xx20 ? 50 ns pic18 lf xx20 ? 100 ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
? 2003 microchip technology inc. ds39599c-page 333 pic18f2220/2320/4220/4320 figure 26-14: example spi ma ster mode timing (cke = 1 ) table 26-15: example spi mode requirements (master mode, cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 26-5 for load conditions. param. no. symbol characteristic min max units conditions 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xx20 ? 25 ns pic18 lf xx20 45 ns 76 t do f sdo data output fall time ? 25 ns 78 t sc r sck output rise time (master mode) pic18 f xx20 ? 25 ns pic18 lf xx20 45 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xx20 ? 50 ns pic18 lf xx20 100 ns 81 t do v2 sc h, t do v2 sc l sdo data output setup to sck edge t cy ?ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used.
pic18f2220/2320/4220/4320 ds39599c-page 334 ? 2003 microchip technology inc. figure 26-15: example spi slave mode timing (cke = 0 ) table 26-16: example spi mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xx20 ? 25 ns pic18 lf xx20 45 ns 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) pic18 f xx20 ? 25 ns pic18 lf xx20 45 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xx20 ? 50 ns pic18 lf xx20 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdi msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in 83 note: refer to figure 26-5 for load conditions.
? 2003 microchip technology inc. ds39599c-page 335 pic18f2220/2320/4220/4320 figure 26-16: example spi slave mode timing (cke = 1 ) table 26-17: example spi slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ss to sck or sck input t cy ?ns 71 t sc h sck input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sck input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ns 75 t do r sdo data output rise time pic18 f xx20 ? 25 ns pic18 lf xx20 45 ns 76 t do f sdo data output fall time ? 25 ns 77 t ss h2 do zss to sdo output high-impedance 10 50 ns 78 t sc r sck output rise time (master mode) pic18 f xx20 ? 25 ns pic18 lf xx20 ? 45 ns 79 t sc f sck output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdo data output valid after sck edge pic18 f xx20 ? 50 ns pic18 lf xx20 ? 100 ns 82 t ss l2 do v sdo data output valid after ss edge pic18 f xx20 ? 50 ns pic18 lf xx20 ? 100 ns 83 tsch2ssh, tscl2ssh ss after sck edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter # 73a. 2: only if parameter # 71a and # 72a are used. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi 70 71 72 82 sdi 74 75, 76 msb bit 6 - - - - - -1 lsb 77 msb in bit 6 - - - -1 lsb in 80 83 note: refer to figure 26-5 for load conditions.
pic18f2220/2320/4220/4320 ds39599c-page 336 ? 2003 microchip technology inc. figure 26-17: i 2 c bus start/stop bits timing table 26-18: i 2 c bus start/stop bits requirements (slave mode) figure 26-18: i 2 c bus data timing note: refer to figure 26-5 for load conditions. 91 92 93 scl sda start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 26-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2003 microchip technology inc. ds39599c-page 337 pic18f2220/2320/4220/4320 table 26-19: i 2 c bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18fxx20 must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18fxx20 must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18fxx20 must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18fxx20 must operate at a minimum of 10 mhz ssp module 1.5 t cy ? 102 t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sda and scl fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provi de this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
pic18f2220/2320/4220/4320 ds39599c-page 338 ? 2003 microchip technology inc. figure 26-19: master ssp i 2 c bus start/stop bits timing waveforms table 26-20: master ssp i 2 c bus start/stop bits requirements figure 26-20: master ssp i 2 c bus data timing note: refer to figure 26-5 for load conditions. 91 93 scl sda start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c pins. note: refer to figure 26-5 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2003 microchip technology inc. ds39599c-page 339 pic18f2220/2320/4220/4320 table 26-21: master ssp i 2 c bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sda and scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sda and scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf note 1: maximum pin capacitance = 10 pf for all i 2 c pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the scl line is released.
pic18f2220/2320/4220/4320 ds39599c-page 340 ? 2003 microchip technology inc. figure 26-21: usart synchronous transmission (master/slave) timing table 26-22: usart synchronous transmission requirements figure 26-22: usart synchronous receive (master/slave) timing table 26-23: usart synchronous receive requirements 121 121 120 122 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 26-5 for load conditions. param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master & slave) clock high to data out valid pic18 f xx20 ? 40 ns pic18 lf xx20 ? 100 ns 121 t ckrf clock out rise time and fall time (master mode) pic18 f xx20 ? 20 ns pic18 lf xx20 ? 50 ns 122 t dtrf data out rise time and fall time pic18 f xx20 ? 20 ns pic18 lf xx20 ? 50 ns 125 126 rc6/tx/ck rc7/rx/dt pin pin note: refer to figure 26-5 for load conditions. param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master & slave) data hold before ck (dt hold time) 10 ? ns 126 t ck l2 dtl data hold after ck (dt hold time) 15 ? ns
? 2003 microchip technology inc. ds39599c-page 341 pic18f2220/2320/4220/4320 table 26-24: a/d converter characteristics: pic18f2220/2320/4220/4320 (industrial) pic18f2220/2320/4220/4320 (extended) pic18lf2220/2320/4220/4320 (industrial) param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bit ? v ref 3.0v a03 e il integral linearity error ? ? <1 lsb ? v ref 3.0v a04 e dl differential linearity error ? ? <1 lsb ? v ref 3.0v a06 e off offset error ? ? <1 lsb ? v ref 3.0v a07 e gn gain error ? ? <1 lsb ? v ref 3.0v a10 ? monotonicity guaranteed (2) ? a20 ? v ref reference voltage range (v refh ? v refl ) 3?av dd ? av ss v for 10-bit resolution a21 v refh reference voltage high av ss + 3.0v ? av dd + 0.3v v for 10-bit resolution a22 v refl reference voltage low av ss ? 0.3v ? av dd ? 3.0v v for 10-bit resolution a25 v ain analog input voltage v refl ?v refh v a28 av dd analog supply voltage v dd ? 0.3 ? v dd + 0.3 v tie to v dd a29 av ss analog supply voltage v ss ? 0.3 ? v ss + 0.3 v tie to v ss a30 z ain recommended impedance of analog voltage source ??2.5 (4) k ? a40 i ad a/d current from v dd pic18 f xx20 ? ? 180 (5) a average current during conversion (1) pic18 lf xx20 ? ? 90 (5) a a50 i ref v ref input current (3) ? ? ? ? 5 (5) 150 (5) a a during v ain acquisition. during a/d conversion cycle. note 1: when a/d is off, it will not consume any current other than minor leakage current. the power-down current spec includes any such leakage from the a/d module. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: v refh current is from ra3/an3/v ref + pin or av dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or av ss , whichever is selected as the v refl source. 4: assume quiet environment. if adjacent pins have high-frequency signals (analog or digital), z ain may need to be reduced to as low as 1 k ? to fight crosstalk effects. 5: for guidance only.
pic18f2220/2320/4220/4320 ds39599c-page 342 ? 2003 microchip technology inc. figure 26-23: a/d conversion timing table 26-25: a/d conversion requirements param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xx20 1.6 20 (2) st osc based, v ref 3.0v pic18 lf xx20 3.0 20 (2) st osc based, v ref full range pic18 f xx20 2.0 6.0 s a/d rc mode pic18 lf xx20 3.0 9.0 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (1) 11 12 t ad note 1: adres register may be read on the following t cy cycle. 2: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy
? 2003 microchip technology inc. ds39599c-page 343 pic18f2220/2320/4220/4320 27.0 dc and ac characteristics graphs and tables ?typical? represents the mean of the distribution at 25 c. ?maximum? or ?minimum? represents (mean + 3 ) or (mean ? 3 ) respectively, where is a standard deviation, over the whole temperature range. figure 27-1: typical i dd vs. f osc over v dd pri_run, ec mode, +25c figure 27-2: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +85c note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 0.0 0.1 0.2 0.3 0.4 0.5 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 344 ? 2003 microchip technology inc. figure 27-3: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 27-4: typical i dd vs. f osc over v dd pri_run, ec mode, +25c 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 345 pic18f2220/2320/4220/4320 figure 27-5: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 27-6: typical i dd vs. f osc over v dd pri_run, ec mode, +25c 0.0 0.5 1.0 1.5 2.0 2.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 346 ? 2003 microchip technology inc. figure 27-7: maximum i dd vs. f osc over v dd pri_run, ec mode, -40c to +125c figure 27-8: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c 0 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 5.0v 5.5v 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 347 pic18f2220/2320/4220/4320 figure 27-9: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +85c figure 27-10: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c 0.000 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0.045 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.000 0.010 0.020 0.030 0.040 0.050 0.060 0.070 0.080 0.090 0.100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 348 ? 2003 microchip technology inc. figure 27-11: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c figure 27-12: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c typical i vs f over v pri_idle, ec mode, +25c 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd ( a) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 100 200 300 400 500 600 1.0 1.5 2.0 2.5 3.0 3.5 4.0 f osc (mhz) i dd ( a) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 349 pic18f2220/2320/4220/4320 figure 27-13: typical i dd vs. f osc over v dd pri_idle, ec mode, +25c figure 27-14: maximum i dd vs. f osc over v dd pri_idle, ec mode, -40c to +125c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 4 8 12 16 20 24 28 32 36 40 f osc (mhz) i dd (ma) 4.0v 4.5v 3.0v 3.5v 2.0v 2.5v 5.0v 5.5v typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 350 ? 2003 microchip technology inc. figure 27-15: typical i pd vs. v dd (+25c), 125 khz to 8 mhz rc_run mode, all peripherals disabled figure 27-16: maximum i pd vs. v dd (-40c to +125c), 125 khz to 8 mhz rc_run, all peripherals disabled 0 500 1000 1500 2000 2500 3000 2.02.53.03.54.04.55.05.5 v dd (v) i pd ( a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz curves. typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 500 1000 1500 2000 2500 3000 3500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz curves. typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 351 pic18f2220/2320/4220/4320 figure 27-17: typical and maximum i pd vs. v dd (-40c to +125c), 31.25 khz rc_run, all peripherals disabled figure 27-18: typical i pd vs. v dd (+25c), 125 khz to 8 mhz rc_idle mode, all peripherals disabled 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz curves. typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 352 ? 2003 microchip technology inc. figure 27-19: maximum i pd vs. v dd (-40c to +125c), 125 khz to 8 mhz rc_idle, all peripherals disabled figure 27-20: typical and maximum i pd vs. v dd (-40c to +125c), 31.25 khz rc_idle, all peripherals disabled 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) 8 mhz 125 khz 4 mhz 2 mhz 1 mhz 250 khz and 500 khz curves are bounded by 125 khz and 1 mhz curves. typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 353 pic18f2220/2320/4220/4320 figure 27-21: i pd sec_run mode, -10c to +70c 32.768 khz xtal 2 x 22 pf, all peripherals disabled figure 27-22: i pd sec_idle, -10c to +70c 32.768 khz 2 x 22 pf, all peripherals disabled 0 10 20 30 40 50 60 70 80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typ (+25c) max (+70c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 16 18 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) typ (+25c) max (+70c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 354 ? 2003 microchip technology inc. figure 27-23: total i pd , -40c to +125c sleep mode, all peripherals disabled figure 27-24: v oh vs. i oh over temperature (-40c to +125c), v dd = 3.0v 0.001 0.01 0.1 1 10 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) i pd ( a) max (+85c) max (+125c) typ (+25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (+125c) min (+125c) typ (+25c)
? 2003 microchip technology inc. ds39599c-page 355 pic18f2220/2320/4220/4320 figure 27-25: v oh vs. i oh over temperature (-40c to +125c), v dd = 5.0v figure 27-26: v ol vs. i ol over temperature (-40c to +125c), v dd = 3.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 i oh (-ma) v oh (v) max (+125c) min (+125c) typ (+25c) v vs i over temp (-40c to +125c) v = 3.0v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (+125c) max (+85c) typ (+25c) min (+125c)
pic18f2220/2320/4220/4320 ds39599c-page 356 ? 2003 microchip technology inc. figure 27-27: v ol vs. i ol over temperature (-40c to +125c), v dd = 5.0v figure 27-28: ? i pd timer1 oscillator, -10c to +70c sleep mode, tmr1 counter disabled 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (-ma) v ol (v) max (+125c) max (+85c) typ (+25c) min (+125c) ipd timer1 oscillator, -10c to +70c sleep mode, tmr1 counter disabled 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.02.53.03.54.04.55.05.5 v dd (v) i pd ( a) typ (+25c) max (-10c to +70c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 357 pic18f2220/2320/4220/4320 figure 27-29: ? i pd f scm vs. v dd over temperature pri_idle, ec oscillator at 32 khz, -40c to +125c figure 27-30: ? i pd wdt, -40c to +125c sleep mode, all peripherals disabled 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i pd ( a) typ (+25c) max (-40c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 2 4 6 8 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) ? i pd ( a) typ (+25c) max (+85c) max (+125c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
pic18f2220/2320/4220/4320 ds39599c-page 358 ? 2003 microchip technology inc. figure 27-31: ? i pd lvd vs. v dd sleep mode, lvd = 2.00v-2.12v figure 27-32: ? i pd bor vs. v dd , -40c to +125c sleep mode, bor enabled at 2.00v-2.16v 0 5 10 15 20 25 30 35 40 45 50 2.02.53.03.54.04.55.05.5 v dd (v) i pd ( a) typ (+25c) max (+85c) max (+125c) low-voltage detection range normal operating range typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0 5 10 15 20 25 30 35 40 2.02.53.03.54.04.55.05.5 v dd (v) i pd ( a) max (+125c) typ (+25c) device may be in reset device is operating typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c)
? 2003 microchip technology inc. ds39599c-page 359 pic18f2220/2320/4220/4320 figure 27-33: ? i pd a/d, -40c to +125c sleep mode, a/d enabled (not converting) figure 27-34: average f osc vs. v dd for various r's external rc mode, c = 20 pf, temperature = +25c 0.001 0.01 0.1 1 10 2.02.53.03.54.04.55.05.5 v dd (v) i pd ( a) max (+125c) max (+85c) typ (+25c) typical: statistical mean @ 25c maximum: mean + 3 (-40c to +125c) minimum: mean ? 3 (-40c to +125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k operation above 4 mhz is not recomended
pic18f2220/2320/4220/4320 ds39599c-page 360 ? 2003 microchip technology inc. figure 27-35: average f osc vs. v dd for various r's external rc mode, c = 100 pf, temperature = +25c figure 27-36: average f osc vs. v dd for various r's external rc mode, c = 300 pf, temperature = +25c 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) freq (mhz) 5.1k 10k 33k 100k
? 2003 microchip technology inc. ds39599c-page 361 pic18f2220/2320/4220/4320 28.0 packaging information 28.1 package marking information 28-lead spdip xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn example pic18f2220-i/sp 0310017 28-lead soic xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx yywwnnn example pic18f2320-e/so 0310017 40-lead pdip xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxx yywwnnn example pic18f4220-i/p 0310017 legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price.
pic18f2220/2320/4220/4320 ds39599c-page 362 ? 2003 microchip technology inc. package marking information (continued) xxxxxxxxxx 44-lead qfn xxxxxxxxxx xxxxxxxxxx yywwnnn pic18f4220 example -i/ml 0310017 44-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example pic18f4320 -i/pt 0310017
? 2003 microchip technology inc. ds39599c-page 363 pic18f2220/2320/4220/4320 28.2 package details the following sections give the technical details of the packages. 28-lead skinny plastic dual in-line (sp) ? 300 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 8.89 8.13 .430 .350 .320 eb overall row spacing 0.56 0.48 0.41 .022 .019 .016 b lower lead width 1.65 1.33 1.02 .065 .053 .040 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.18 .135 .130 .125 l tip to seating plane 35.18 34.67 34.16 1.385 1.365 1.345 d overall length 7.49 7.24 6.99 .295 .285 .275 e1 molded package width 8.26 7.87 7.62 .325 .310 .300 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.43 3.30 3.18 .135 .130 .125 a2 molded package thickness 4.06 3.81 3.56 .160 .150 .140 a top to seating plane 2.54 .100 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n e1 c eb e p l a2 b b1 a a1 notes: jedec equivalent: mo-095 drawing no. c04-070 * controlling parameter dimension d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. significant characteristic
pic18f2220/2320/4220/4320 ds39599c-page 364 ? 2003 microchip technology inc. 28-lead plastic small outline (so) ? wide, 300 mil (soic) foot angle top 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 18.08 17.87 17.65 .712 .704 .695 d overall length 7.59 7.49 7.32 .299 .295 .288 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 28 28 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d p n b e e1 l c 45 h a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-052 significant characteristic
? 2003 microchip technology inc. ds39599c-page 365 pic18f2220/2320/4220/4320 40-lead plastic dual in-line (p) ? 600 mil (pdip) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 17.27 16.51 15.75 .680 .650 .620 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.78 1.27 0.76 .070 .050 .030 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.43 3.30 3.05 .135 .130 .120 l tip to seating plane 52.45 52.26 51.94 2.065 2.058 2.045 d overall length 14.22 13.84 13.46 .560 .545 .530 e1 molded package width 15.88 15.24 15.11 .625 .600 .595 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 4.06 3.81 3.56 .160 .150 .140 a2 molded package thickness 4.83 4.45 4.06 .190 .175 .160 a top to seating plane 2.54 .100 p pitch 40 40 n number of pins max nom min max nom min dimension limits millimeters inches* units a2 1 2 d n e1 c eb e p l b b1 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: mo-011 drawing no. c04-016 significant characteristic
pic18f2220/2320/4220/4320 ds39599c-page 366 ? 2003 microchip technology inc. 44-lead plastic thin quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) * controlling parameter notes: dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-026 drawing no. c04-076 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 .039 (f) footprint (reference) (f) a a1 a2 e e1 #leads=n1 p b d1 d n 1 2 c l units inches millimeters* dimension limits min nom max min nom max number of pins n 44 44 pitch p .031 0.80 overall height a .039 .043 .047 1.00 1.10 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 03.5 7 03.5 7 overall width e .463 .472 .482 11.75 12.00 12.25 overall length d .463 .472 .482 11.75 12.00 12.25 molded package width e1 .390 .394 .398 9.90 10.00 10.10 molded package length d1 .390 .394 .398 9.90 10.00 10.10 pins per side n1 11 11 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .012 .015 .017 0.30 0.38 0.44 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 ch x 45 significant characteristic
? 2003 microchip technology inc. ds39599c-page 367 pic18f2220/2320/4220/4320 44-lead plastic quad flat no lead package (ml) 8x8 mm body (qfn) contact width *controlling parameter drawing no. c04-103 notes: 1. 2. b .008 .013 .013 0.20 0.33 0.35 pitch number of contacts overall width standoff overall length overall height max units dimension limits a1 d e n p a .000 inches .026 bsc min 44 nom max .002 0 millimeters* .039 min 44 0.65 bsc nom 0.05 1.00 .010 ref base thickness (a3) 0.25 ref 4. 0.90 .035 .001 0.02 .315 8.00 contact length l .014 .016 .019 0.35 0.40 0.48 e2 d2 exposed pad width exposed pad length .246 .268 .274 6.25 6.80 6.95 .246 .268 .274 6.25 6.80 6.95 d2 d a1 (a3) a top view n 1 l e2 bottom view b e 2 pad metal exposed p pin 1 index on exposed pad top marking index on optional pin 1 .031 0.80 detail: contact variants 7.85 8.15 .321 .309 .309 .315 8.00 7.85 .321 8.15 22 11 bsc: basic dimension. theoretically exact value shown without tolerances. jedec equivalent: m0-220 ref: reference dimension, usually without tolerance, for information purposes only. see asme y14.5m see asme y14.5m 3. contact profiles may vary. (profile may vary)
pic18f2220/2320/4220/4320 ds39599c-page 368 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 369 pic18f2220/2320/4220/4320 appendix a: revision history revision a (june 2002) original data sheet for pic18f2x20/4x20 devices. revision b (october 2002) this revision includes major changes to section 2.0 ?oscillator configurations? and section 3.0 ?power managed modes? , updates to the electrical specifica- tions in section 26.0 ?electrical characteristics? and minor corrections to the data sheet text. revision c (october 2003) this revision includes updates to the electrical specifi- cations in section 26.0 ?electrical characteristics? and to the dc characteristics graphs and charts in section 27.0 ?dc and ac characteristics graphs and tables? and minor corrections to the data sheet text. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences features pic18f2220 pic18f2320 pic18f4220 pic18f4320 program memory (bytes) 4096 8192 4096 8192 program memory (instructions) 2048 4096 2048 4096 interrupt sources 19 19 20 20 i/o ports ports a, b, c, (e) ports a, b, c, (e) ports a, b, c, d, e ports a, b, c, d, e capture/compare/pwm modules 2 2 1 1 enhanced capture/compare/ pwm modules 0011 parallel communications (psp) no no yes yes 10-bit analog-to-digital module 10 input channels 10 input channels 13 input channels 13 input channels packages 28-pin spdip 28-pin soic 28-pin spdip 28-pin soic 40-pin pdip 44-pin tqfp 44-pin qfn 40-pin pdip 44-pin tqfp 44-pin qfn
pic18f2220/2320/4220/4320 ds39599c-page 370 ? 2003 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for con- verting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available
? 2003 microchip technology inc. ds39599c-page 371 pic18f2220/2320/4220/4320 appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442.? the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration.? this application note is available as literature number ds00726.
pic18f2220/2320/4220/4320 ds39599c-page 372 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 373 pic18f2220/2320/4220/4320 index a a/d ................................................................................... 211 a/d converter interrupt, configuring ....................... 215 acquisition requirements ........................................ 216 adcon0 register .................................................... 211 adcon1 register .................................................... 211 adcon2 register .................................................... 211 adresh register ............................................ 211 , 214 adresl register .................................................... 211 analog port pins, configuring .................................. 218 associated registers ............................................... 220 automatic acquisition time ...................................... 217 calculating the minimum required acquisition time ............................................... 216 configuring the module ............................................ 215 conversion clock (t ad ) ........................................... 217 conversion status (go/done bit) .......................... 214 conversions ............................................................. 219 converter characteristics ........................................ 341 operation in power managed modes ...................... 218 special event trigger (ccp) ............................ 136 , 220 use of the ccp2 trigger .......................................... 220 v ref + and v ref - references .................................. 216 absolute maximum ratings ............................................. 305 ac (timing) characteristics ............................................. 323 load conditions for device timing specifications ....................................... 324 parameter symbology ............................................. 323 temperature and voltage specifications ................. 324 timing conditions .................................................... 324 access bank ...................................................................... 65 ackstat status flag ..................................................... 185 adcon0 register ............................................................ 211 go/done bit ........................................................... 214 adcon1 register ............................................................ 211 adcon2 register ............................................................ 211 addlw ............................................................................ 261 addressable universal synchronous asynchronous receiver transmitter. see usart. addwf ............................................................................ 261 addwfc ......................................................................... 262 adresh register ............................................................ 211 adresl register .................................................... 211 , 214 analog-to-digital converter. see a/d. andlw ............................................................................ 262 andwf ............................................................................ 263 assembler mpasm assembler .................................................. 299 b bank select register (bsr) ............................................... 65 baud rate generator ....................................................... 181 bc .................................................................................... 263 bcf .................................................................................. 264 bf status flag ................................................................. 185 block diagrams a/d ........................................................................... 214 analog input model .................................................. 215 baud rate generator ............................................... 181 capture mode operation ......................................... 135 comparator i/o operating modes ............................ 222 comparator output .................................................. 224 comparator voltage reference ............................... 228 compare mode operation ....................................... 136 external power-on reset circuit (slow v dd power-up) ........................................ 44 fail-safe clock monitor ........................................... 248 generic i/o port operation ...................................... 101 interrupt logic ............................................................ 88 low-voltage detect (lvd) ....................................... 232 low-voltage detect (lvd) with external input ........ 232 mclr /v pp /re3 pin ................................................. 111 mssp (i 2 c master mode) ........................................ 179 mssp (i 2 c mode) .................................................... 164 mssp (spi mode) ................................................... 155 on-chip reset circuit ................................................ 43 pic18f2220/2320 ....................................................... 9 pic18f4220/4320 ..................................................... 10 pll ............................................................................ 20 portc (peripheral output override) ...................... 107 portd and porte (parallel slave port) ............... 114 pwm (enhanced) .................................................... 143 pwm (standard) ...................................................... 138 ra3:ra0 and ra5 pins ........................................... 102 ra4/t0cki pin ........................................................ 102 ra6 pin ................................................................... 102 ra7 pin ................................................................... 102 rb2:rb0 pins .......................................................... 105 rb3/ccp2 pin ......................................................... 105 rb4 pin ................................................................... 105 rb7:rb5 pins .......................................................... 104 rd4:rd0 pins ......................................................... 110 rd7:rd5 pins ......................................................... 109 re2:re0 pins .......................................................... 111 reads from flash program memory .......................... 75 system clock ............................................................. 25 table read operation ............................................... 71 table write operation ................................................ 72 table writes to flash program memory .................... 77 timer0 in 16-bit mode .............................................. 118 timer0 in 8-bit mode ................................................ 118 timer1 ..................................................................... 122 timer1 (16-bit read/write mode) ............................ 122 timer2 ..................................................................... 128 timer3 ..................................................................... 130 timer3 (16-bit read/write mode) ............................ 130 usart receive ....................................................... 204 usart transmit ...................................................... 202 watchdog timer ...................................................... 245 bn .................................................................................... 264 bnc ................................................................................. 265 bnn ................................................................................. 265 bnov ............................................................................... 266 bnz .................................................................................. 266 bor. see brown-out reset. bov ................................................................................. 269 bra ................................................................................. 267 brg. see baud rate generator. brown-out reset (bor) ..............................................44 , 237 bsf .................................................................................. 267 btfsc ............................................................................. 268 btfss ............................................................................. 268 btg ................................................................................. 269 bz .................................................................................... 270
pic18f2220/2320/4220/4320 ds39599c-page 374 ? 2003 microchip technology inc. c c compilers mplab c17 ............................................................. 300 mplab c18 ............................................................. 300 mplab c30 ............................................................. 300 call ................................................................................ 270 capture (ccp module) ..................................................... 135 associated registers ............................................... 137 ccp pin configuration ............................................. 135 ccpr1h:ccpr1l registers ................................... 135 software interrupt ..................................................... 135 timer1/timer3 mode selection ................................ 135 capture (eccp module) .................................................. 142 capture/compare/pwm (ccp) ........................................ 133 capture mode. see capture. ccp1 ........................................................................ 134 ccpr1h register ............................................ 134 ccpr1l register ............................................ 134 ccp2 ........................................................................ 134 ccpr2h register ............................................ 134 ccpr2l register ............................................ 134 compare mode. see compare. interaction of two ccp modules ............................. 134 pwm mode. see pwm. timer resources ...................................................... 134 clock sources .................................................................... 24 selection using osccon register ........................... 24 clocking scheme/instruction cycle .................................... 57 clrf ................................................................................ 271 clrwdt .......................................................................... 271 code examples 16 x 16 signed multiply routine ................................. 86 16 x 16 unsigned multiply routine ............................. 86 8 x 8 signed multiply routine ..................................... 85 8 x 8 unsigned multiply routine ................................. 85 changing between capture prescalers ................... 135 computed goto using an offset value ................... 59 data eeprom read ................................................. 83 data eeprom refresh routine ................................ 84 data eeprom write .................................................. 83 erasing a flash program memory row ..................... 76 fast register stack .................................................... 56 how to clear ram (bank 1) using indirect addressing ............................................ 66 implementing a real-time clock using a timer1 interrupt service .................................. 125 initializing porta .................................................... 101 initializing portb .................................................... 104 initializing portc .................................................... 107 initializing portd .................................................... 109 initializing porte .................................................... 111 loading the sspbuf (sspsr) register ................. 158 reading a flash program memory word ................... 75 saving status, wreg and bsr registers in ram ............................................................... 99 writing to flash program memory ....................... 78 ? 79 code protection ....................................................... 237 , 251 comf ............................................................................... 272 comparator ...................................................................... 221 analog input connection considerations ................ 225 associated registers ............................................... 226 configuration ........................................................... 221 effects of a reset .................................................... 225 interrupts .................................................................. 224 operation ................................................................. 223 operation in power managed modes ...................... 225 outputs .................................................................... 223 reference ................................................................ 223 response time ........................................................ 223 comparator specifications ............................................... 321 comparator voltage reference ....................................... 227 accuracy and error .................................................. 228 associated registers ............................................... 229 configuring .............................................................. 227 connection considerations ...................................... 228 effects of a reset .................................................... 228 operation in power managed modes ...................... 228 compare (ccp module) .................................................. 136 associated registers ............................................... 137 ccp pin configuration ............................................. 136 ccpr1 register ...................................................... 136 software interrupt .................................................... 136 special event trigger .......................................136 , 220 timer1/timer3 mode selection ................................ 136 compare (eccp mode) ................................................... 142 computed goto ............................................................... 59 configuration bits ............................................................ 237 configuration register protection .................................... 254 context saving during interrupts ....................................... 99 control registers eecon1 and eecon2 ............................................. 72 conversion considerations .............................................. 370 cpfseq .......................................................................... 272 cpfsgt .......................................................................... 273 cpfslt ........................................................................... 273 crystal oscillator/ ceramic resonator ................................ 19 d data eeprom code protection ...................................... 254 data eeprom memory ..................................................... 81 associated registers ................................................. 84 eeadr register ........................................................ 81 eecon1 and eecon2 registers ............................. 81 operation during code-protect ................................. 84 protection against spurious write ............................. 83 reading ..................................................................... 83 using .......................................................................... 84 write verify ................................................................ 83 writing ........................................................................ 83 data memory ..................................................................... 59 general purpose registers ....................................... 59 map for pic18f2x20/4x20 ........................................ 60 special function registers ........................................ 61 daw ................................................................................ 274 dc and ac characteristics graphs and tables .................................................. 343 dc characteristics ........................................................... 318 power-down and supply current ............................ 309 supply voltage ......................................................... 308 dcfsnz .......................................................................... 275 decf ............................................................................... 274 decfsz .......................................................................... 275
? 2003 microchip technology inc. ds39599c-page 375 pic18f2220/2320/4220/4320 demonstration boards picdem 1 ................................................................ 302 picdem 17 .............................................................. 302 picdem 18r pic18c601/801 ................................. 303 picdem 2 plus ........................................................ 302 picdem 3 pic16c92x ............................................ 302 picdem 4 ................................................................ 302 picdem lin pic16c43x ........................................ 303 picdem usb pic16c7x5 ....................................... 303 picdem.net internet/ethernet ................................. 302 development support ...................................................... 299 device differences ........................................................... 369 device overview .................................................................. 7 features (table) ............................................................ 8 new core features ...................................................... 7 other special features ................................................ 7 direct addressing ............................................................... 67 e eccp ............................................................................... 141 auto-shutdown ........................................................ 149 and automatic restart ..................................... 151 capture and compare modes .................................. 142 outputs .................................................................... 142 standard pwm mode ............................................... 142 start-up considerations ........................................... 151 effects of power managed modes on various clock sources ............................................... 27 electrical characteristics .................................................. 305 enhanced capture/compare/pwm (eccp) .................... 141 capture mode. see capture (eccp module). pwm mode. see pwm (eccp module). enhanced ccp auto-shutdown ....................................... 149 enhanced pwm mode. see pwm (eccp module). equations 16 x 16 signed multiplication algorithm ..................... 86 16 x 16 unsigned multiplication algorithm ................. 86 a/d acquisition time ................................................ 216 a/d minimum holding capacitor .............................. 216 errata ................................................................................... 5 evaluation and programming tools ................................. 303 external clock input ........................................................... 21 f fail-safe clock monitor ............................................ 237 , 248 interrupts in power managed modes ....................... 250 por or wake-up from sleep ................................... 250 wdt during oscillator failure ................................. 248 fast register stack ............................................................ 56 firmware instructions ....................................................... 255 flash program memory ...................................................... 71 associated registers ................................................. 79 control registers ....................................................... 72 erase sequence ........................................................ 76 erasing ....................................................................... 76 operation during code-protect ................................. 79 reading ...................................................................... 75 tablat register ....................................................... 74 table pointer .............................................................. 74 boundaries based on operation ........................ 74 table pointer boundaries .......................................... 74 table reads and table writes .................................. 71 unexpected termination of write operation .............. 79 write verify ................................................................ 79 writing to .................................................................... 77 fscm. see fail-safe clock monitor. g goto .............................................................................. 276 h hardware multiplier ............................................................ 85 introduction ................................................................ 85 operation ................................................................... 85 performance comparison .......................................... 85 hspll ............................................................................... 20 i i/o ports ........................................................................... 101 i 2 c mode ack pulse ........................................................168 , 169 acknowledge sequence timing .............................. 188 baud rate generator .............................................. 181 bus collision during a repeated start condition ................................................. 192 bus collision during a start condition ..................... 190 bus collision during a stop condition ..................... 193 clock arbitration ...................................................... 182 clock stretching ....................................................... 174 effect of a reset ...................................................... 189 general call address support ................................. 178 master mode ............................................................ 179 master mode (reception, 7-bit address) ................. 187 master mode operation ........................................... 180 master mode reception ........................................... 185 master mode repeated start condition timing .............................................. 184 master mode start condition timing ....................... 183 master mode transmission ..................................... 185 multi-master communication, bus collision and bus arbitration .......................................... 189 multi-master mode ................................................... 189 operation ................................................................. 168 operation in power managed mode ........................ 189 read/write bit information (r/w bit) ................168 , 169 registers ................................................................. 164 serial clock (rc3/sck/scl) ................................... 169 slave mode .............................................................. 168 addressing ....................................................... 168 reception ........................................................ 169 transmission ................................................... 169 stop condition timing ............................................. 188 id locations ..............................................................237 , 254 incf ................................................................................ 276 incfsz ............................................................................ 277 in-circuit debugger .......................................................... 254 in-circuit serial programming (icsp) .......................237 , 254 indirect addressing indf and fsr registers ........................................... 66 operation ................................................................... 66 indirect addressing operation ........................................... 67 indirect file operand ......................................................... 59 infsnz ............................................................................ 277 initialization conditions for all registers .......................46 ? 49 instruction cycle ................................................................ 57 instruction flow/pipelining ................................................. 57 instruction format ............................................................ 257
pic18f2220/2320/4220/4320 ds39599c-page 376 ? 2003 microchip technology inc. instruction set .................................................................. 255 addlw .................................................................... 261 addwf .................................................................... 261 addwfc ................................................................. 262 andlw .................................................................... 262 andwf .................................................................... 263 bc ............................................................................ 263 bcf .......................................................................... 264 bn ............................................................................ 264 bnc .......................................................................... 265 bnn .......................................................................... 265 bnov ....................................................................... 266 bnz .......................................................................... 266 bov .......................................................................... 269 bra .......................................................................... 267 bsf .......................................................................... 267 btfsc ..................................................................... 268 btfss ...................................................................... 268 btg .......................................................................... 269 bz ............................................................................. 270 call ........................................................................ 270 clrf ........................................................................ 271 clrwdt .................................................................. 271 comf ....................................................................... 272 cpfseq .................................................................. 272 cpfsgt ................................................................... 273 cpfslt ................................................................... 273 daw ......................................................................... 274 dcfsnz ................................................................... 275 decf ....................................................................... 274 decfsz ................................................................... 275 goto ....................................................................... 276 incf ......................................................................... 276 incfsz .................................................................... 277 infsnz .................................................................... 277 iorlw ..................................................................... 278 iorwf ..................................................................... 278 lfsr ........................................................................ 279 movf ....................................................................... 279 movff ..................................................................... 280 movlb ..................................................................... 280 movlw .................................................................... 281 movwf ................................................................... 281 mullw .................................................................... 282 mulwf .................................................................... 282 negf ....................................................................... 283 nop ......................................................................... 283 pop .......................................................................... 284 push ....................................................................... 284 rcall ...................................................................... 285 reset ........................................................................ 285 retfie .................................................................... 286 retlw ..................................................................... 286 return .................................................................. 287 rlcf ........................................................................ 287 rlncf ..................................................................... 288 rrcf ....................................................................... 288 rrncf ..................................................................... 289 setf ........................................................................ 289 sleep ...................................................................... 290 subfwb .................................................................. 290 sublw .................................................................... 291 subwf .................................................................... 291 subwfb ................................................................. 292 swapf .................................................................... 293 tblrd ..................................................................... 294 tblwt ..................................................................... 295 tstfsz ................................................................... 296 xorlw .................................................................... 296 xorwf ................................................................... 297 summary table ....................................................... 258 intcon register rbif bit ................................................................... 104 intcon registers ............................................................. 89 inter-integrated circuit. see i 2 c. internal oscillator block ..................................................... 22 adjustment ................................................................. 22 intio modes ............................................................. 22 intrc output frequency .......................................... 22 osctune register ................................................... 22 internal rc oscillator use with wdt .......................................................... 245 interrupt sources ............................................................. 237 a/d conversion complete ....................................... 215 capture complete (ccp) ......................................... 135 compare complete (ccp) ....................................... 136 interrupt-on-change (rb7:rb4) .............................. 104 intn pin ..................................................................... 99 portb, interrupt-on-change .................................... 99 tmr0 ......................................................................... 99 tmr1 overflow ........................................................ 121 tmr2 to pr2 match ................................................ 128 tmr2 to pr2 match (pwm) .............................127 , 138 tmr3 overflow .................................................129 , 131 usart receive/transmit complete ....................... 195 interrupts ............................................................................ 87 interrupts, enable bits ccp1 enable (ccp1ie bit) ..................................... 135 interrupts, flag bits ccp1 flag (ccp1if bit) .......................................... 135 ccp1if flag (ccp1if bit) ....................................... 136 interrupt-on-change (rb7:rb4) flag (rbif bit) ..... 104 intosc frequency drift .................................................... 40 intosc, intrc. see internal oscillator block. iorlw ............................................................................. 278 iorwf ............................................................................. 278 ipr registers ..................................................................... 96 l lfsr ................................................................................ 279 look-up tables .................................................................. 59 low-voltage detect ......................................................... 231 characteristics ......................................................... 322 effects of a reset .................................................... 235 operation ................................................................. 234 current consumption ....................................... 235 reference voltage set point ........................... 235 operation during sleep ........................................... 235 low-voltage icsp programming ..................................... 254 lvd. see low-voltage detect.
? 2003 microchip technology inc. ds39599c-page 377 pic18f2220/2320/4220/4320 m master synchronous serial port (mssp). see mssp. memory organization ......................................................... 53 data memory ............................................................. 59 program memory ....................................................... 53 memory programming requirements .............................. 320 migration from baseline to enhanced devices ................ 370 migration from high-end to enhanced devices ............... 371 migration from mid-range to enhanced devices ............. 371 movf ............................................................................... 279 movff ............................................................................. 280 movlb ............................................................................. 280 movlw ............................................................................ 281 movwf ........................................................................... 281 mplab asm30 assembler, linker, librarian .................. 300 mplab icd 2 in-circuit debugger ................................... 301 mplab ice 2000 high performance universal in-circuit emulator ................................... 301 mplab ice 4000 high performance universal in-circuit emulator ................................... 301 mplab integrated development environment software .............................................. 299 mplink object linker/mplib object librarian ............... 300 mssp ............................................................................... 155 control registers (general) ..................................... 155 enabling spi i/o ...................................................... 159 i 2 c master mode ...................................................... 179 i 2 c mode i 2 c slave mode ........................................................ 168 operation ................................................................. 158 overview .................................................................. 155 slave select control ................................................ 161 spi master mode ..................................................... 160 spi master/slave connection .................................. 159 spi mode ................................................................. 155 spi slave mode ....................................................... 161 typical connection .................................................. 159 mullw ............................................................................ 282 mulwf ............................................................................ 282 n negf ............................................................................... 283 nop ................................................................................. 283 o opcode field descriptions ............................................... 256 option_reg register psa bit ..................................................................... 119 t0cs bit ................................................................... 119 t0ps2:t0ps0 bits ................................................... 119 t0se bit ................................................................... 119 oscillator configuration ...................................................... 19 ec .............................................................................. 19 ecio .......................................................................... 19 hs .............................................................................. 19 hspll ........................................................................ 19 internal oscillator block ............................................. 22 intio1 ....................................................................... 19 intio2 ....................................................................... 19 lp ............................................................................... 19 rc .............................................................................. 19 rcio .......................................................................... 19 xt .............................................................................. 19 oscillator selection .......................................................... 237 oscillator start-up timer (ost) ............................ 27 , 44 , 237 oscillator switching ........................................................... 24 oscillator transitions ......................................................... 27 oscillator, timer1 ......................................................121 , 131 oscillator, timer3 ............................................................. 129 p packaging information ..................................................... 361 marking .............................................................361 , 362 parallel slave port (psp) ..........................................109 , 114 associated registers ............................................... 115 cs (chip select) ...............................................113 , 114 portd .................................................................... 114 rd (read input) ................................................113 , 114 re0/an5/rd pin ..................................................... 113 re1/an6/wr pin ..................................................... 113 re2/an7/cs pin ...................................................... 113 select (pspmode bit) .....................................109 , 114 wr (write input) ...............................................113 , 114 pickit 1 flash starter kit ................................................. 303 picstart plus development programmer .................... 301 pie registers ..................................................................... 94 pin functions mclr /v pp /re3 ....................................................11 , 14 osc1/clki/ra7 ...................................................11 , 14 osc2/clko/ra6 .................................................11 , 14 ra0/an0 ...............................................................11 , 14 ra1/an1 ...............................................................11 , 14 ra2/an2/v ref -/cv ref .........................................11 , 14 ra3/an3/v ref + ...................................................11 , 14 ra4/t0cki/c1out ..............................................11 , 14 ra5/an4/ss /lvdin/c2out ................................11 , 14 rb0/an12/int0 ....................................................12 , 15 rb1/an10/int1 ....................................................12 , 15 rb2/an8/int2 ......................................................12 , 15 rb3/an9/ccp2 ....................................................12 , 15 rb4/an11/kbi0 ....................................................12 , 15 rb5/kbi1/pgm .....................................................12 , 15 rb6/kbi2/pgc .....................................................12 , 15 rb7/kbi3/pgd .......................................................... 12 rb7/pgd ................................................................... 15 rc0/t1oso/t1cki ..............................................13 , 16 rc1/t1osi/ccp2 .................................................13 , 16 rc2/ccp1/p1a ....................................................13 , 16 rc3/sck/scl ......................................................13 , 16 rc4/sdi/sda .......................................................13 , 16 rc5/sdo ..............................................................13 , 16 rc6/tx/ck ...........................................................13 , 16 rc7/rx/dt ...........................................................13 , 16 rd0/psp0 ................................................................. 17 rd1/psp1 ................................................................. 17 rd2/psp2 ................................................................. 17 rd3/psp3 ................................................................. 17 rd4/psp4 ................................................................. 17 rd5/psp5/p1b ......................................................... 17 rd6/psp6/p1c ......................................................... 17 rd7/psp7/p1d ......................................................... 17 re0/an5/rd .............................................................. 18 re1/an6/wr ............................................................. 18 re2/an7/cs .............................................................. 18 re3 ............................................................................ 18 v dd .......................................................................13 , 18 v ss .......................................................................13 , 18
pic18f2220/2320/4220/4320 ds39599c-page 378 ? 2003 microchip technology inc. pinout i/o descriptions pic18f2220/2320 ...................................................... 11 pic18f4220/4320 ...................................................... 14 pir registers ..................................................................... 92 pll lock time-out ............................................................. 44 pointer, fsrn ..................................................................... 66 pop .................................................................................. 284 por. see power-on reset. porta associated registers ............................................... 103 lata register .......................................................... 101 porta register ...................................................... 101 trisa register ........................................................ 101 portb associated registers ............................................... 106 latb register .......................................................... 104 portb register ...................................................... 104 rb7:rb4 interrupt-on-change flag (rbif bit) ........ 104 trisb register ........................................................ 104 portc associated registers ............................................... 108 latc register .......................................................... 107 portc register ...................................................... 107 trisc register ........................................................ 107 portd associated registers ............................................... 110 latd register .......................................................... 109 parallel slave port (psp) function .......................... 109 portd register ...................................................... 109 trisd register ........................................................ 109 porte analog port pins ...................................................... 113 associated registers ............................................... 113 late register .......................................................... 111 porte register ...................................................... 111 psp mode select (pspmode bit) .......................... 109 re0/an5/rd pin ...................................................... 113 re1/an6/wr pin ..................................................... 113 re2/an7/cs pin ...................................................... 113 trise register ........................................................ 111 postscaler, wdt assignment (psa bit) ............................................... 119 rate select (t0ps2:t0ps0 bits) ............................. 119 power managed modes ..................................................... 29 entering ...................................................................... 30 idle modes .................................................................. 31 run modes ................................................................. 36 selecting .................................................................... 29 sleep mode ................................................................ 31 summary (table) ......................................................... 29 wake-up from ............................................................. 38 power-on reset (por) .............................................. 44 , 237 power-up delays ................................................................ 27 power-up timer (pwrt) ...................................... 27 , 44 , 237 prescaler, capture ........................................................... 135 prescaler, timer0 ............................................................. 119 assignment (psa bit) ............................................... 119 rate select (t0ps2:t0ps0 bits) ............................. 119 prescaler, timer2 ............................................................. 139 pro mate ii universal device programmer ................... 301 product identification system ........................................... 385 program counter pcl register .............................................................. 56 pclath register ....................................................... 56 pclatu register ....................................................... 56 program memory instructions ................................................................ 58 two-word .......................................................... 58 interrupt vector .......................................................... 53 map and stack for pic18f2220/4220 ....................... 53 map and stack for pic18f2320/4320 ....................... 53 reset vector .............................................................. 53 program memory code protection .................................. 252 program verification ........................................................ 251 program verification and code protection associated registers ............................................... 251 programming, device instructions ................................... 255 psp. see parallel slave port. pulse width modulation. see pwm (ccp module) and pwm (eccp module). push ............................................................................... 284 push and pop instructions .............................................. 55 pwm (ccp module) ........................................................ 138 associated registers ............................................... 139 ccpr1h:ccpr1l registers ................................... 138 duty cycle ............................................................... 138 example frequencies/resolutions .......................... 139 period ...................................................................... 138 setup for pwm operation ........................................ 139 tmr2 to pr2 match .........................................127 , 138 pwm (eccp module) ...................................................... 143 associated registers ............................................... 153 direction change in full-bridge output mode ......... 147 effects of a reset .................................................... 152 full-bridge application example .............................. 147 full-bridge mode ..................................................... 146 half-bridge mode ..................................................... 145 half-bridge output mode applications example ...... 145 operation in power managed modes ...................... 152 operation with fail-safe clock monitor ................... 152 output configurations .............................................. 143 output relationships (active-high state) ................ 144 output relationships (active-low state) ................. 144 programmable dead band delay ............................ 149 setup for operation ................................................. 152 shoot-through current ............................................ 149 start-up considerations ........................................... 151 q q clock ............................................................................ 139 r ram. see data memory. rc oscillator ...................................................................... 21 rcio oscillator mode ................................................ 21 rcall ............................................................................. 285 rcon register bit status during initialization .................................... 45 bits and positions ...................................................... 45 rcsta register spen bit .................................................................. 195 register file ....................................................................... 59 registers adcon0 (a/d control 0) ......................................... 211 adcon1 (a/d control 1) ......................................... 212 adcon2 (a/d control 2) ......................................... 213 ccp1con (enhanced ccp operation control 1) ........................................ 141 ccpxcon (capture/compare/pwm control) ......... 133 cmcon (comparator control) ................................ 221 config1h (configuration 1 high) .......................... 238
? 2003 microchip technology inc. ds39599c-page 379 pic18f2220/2320/4220/4320 config2h (configuration 2 high) .......................... 239 config2l (configuration 2 low) ............................ 239 config3h (configuration 3 high) .......................... 240 config4l (configuration 4 low) ............................ 240 config5h (configuration 5 high) .......................... 241 config5l (configuration 5 low) ............................ 241 config6h (configuration 6 high) .......................... 242 config6l (configuration 6 low) ............................ 242 config7h (configuration 7 high) .......................... 243 config7l (configuration 7 low) ............................ 243 cvrcon (comparator voltage reference control) ........................................... 227 device id register 1 ................................................ 244 device id register 2 ................................................ 244 eccpas (enhanced ccp auto-shutdown control) ................................... 150 eecon1 (data eeprom control 1) ................... 73 , 82 intcon (interrupt control) ........................................ 89 intcon2 (interrupt control 2) ................................... 90 intcon3 (interrupt control 3) ................................... 91 ipr1 (peripheral interrupt priority 1) .......................... 96 ipr2 (peripheral interrupt priority 2) .......................... 97 lvdcon (lvd control) ........................................... 233 osccon (oscillator control) .................................... 26 osctune (oscillator tuning) ................................... 23 pie1 (peripheral interrupt enable 1) .......................... 94 pie2 (peripheral interrupt enable 2) .......................... 95 pir1 (peripheral interrupt request (flag) 1) ............................................................. 92 pir2 (peripheral interrupt request (flag) 2) ............................................................. 93 pwm1con (enhanced pwm configuration) ........... 149 rcon (reset control) ......................................... 69 , 98 rcsta (receive status and control) ...................... 197 sspcon1 (mssp control 1, i 2 c mode) ................. 166 sspcon1 (mssp control 1, spi mode) ................. 157 sspcon2 (mssp control 2, i 2 c mode) ................. 167 sspstat (mssp status, i 2 c mode) ....................... 165 sspstat (mssp status, spi mode) ...................... 156 status ......................................................................... 68 stkptr (stack pointer) ............................................ 55 summary .............................................................. 62 ? 64 t0con (timer0 control) .......................................... 117 t1con (timer 1 control) ......................................... 121 t2con (timer 2 control) ......................................... 127 t3con (timer3 control) .......................................... 129 trise ...................................................................... 112 txsta (transmit status and control) ..................... 196 wdtcon (watchdog timer control) ....................... 246 reset .......................................................................... 43 , 285 resets .............................................................................. 237 retfie ............................................................................ 286 retlw ............................................................................. 286 return .......................................................................... 287 return address stack ........................................................ 54 return stack pointer (stkptr) ........................................ 54 revision history ............................................................... 369 rlcf ................................................................................ 287 rlncf ............................................................................. 288 rrcf ............................................................................... 288 rrncf ............................................................................. 289 s sci. see usart. sck ................................................................................. 155 sdi ................................................................................... 155 sdo ................................................................................. 155 serial clock (sck) pin ..................................................... 155 serial communication interface. see usart. serial data in (sdi) pin ................................................... 155 serial data out (sdo) pin ............................................... 155 serial peripheral interface. see spi mode. setf ................................................................................ 289 shoot-through current .................................................... 149 slave select (ss ) pin ...................................................... 155 sleep ............................................................................. 290 sleep osc1 and osc2 pin states ...................................... 27 software simulator (mplab sim) ................................... 300 software simulator (mplab sim30) ............................... 300 special event trigger. see compare (ccp module) special features of the cpu ........................................... 237 special function registers ................................................ 61 map ............................................................................ 61 spi mode associated registers ............................................... 163 bus mode compatibility ........................................... 163 effects of a reset .................................................... 163 master in power managed modes ........................... 163 master mode ............................................................ 160 master/slave connection ......................................... 159 registers ................................................................. 156 serial clock .............................................................. 155 serial data in ........................................................... 155 serial data out ........................................................ 155 slave in power managed modes ............................. 163 slave mode .............................................................. 161 slave select ............................................................. 155 spi clock ................................................................. 160 ss .................................................................................... 155 ssp i 2 c mode. see i 2 c. sspbuf register .................................................... 160 sspsr register ...................................................... 160 tmr2 output for clock shift .............................127 , 128 sspov status flag ......................................................... 185 sspstat register r/w bit .............................................................168 , 169 stack full/underflow resets .............................................. 55 subfwb ......................................................................... 290 sublw ............................................................................ 291 subwf ............................................................................ 291 subwfb ......................................................................... 292 swapf ............................................................................ 293 t tablat register ............................................................... 74 table pointer operations (table) ........................................ 74 table reads/table writes ................................................. 59 tblptr register ............................................................... 74 tblrd ............................................................................. 294 tblwt ............................................................................. 295 time-out in various situations (table) ................................ 45 time-out sequence ........................................................... 44
pic18f2220/2320/4220/4320 ds39599c-page 380 ? 2003 microchip technology inc. timer0 .............................................................................. 117 16-bit mode timer reads and writes ...................... 119 associated registers ............................................... 119 clock source edge select (t0se bit) ...................... 119 clock source select (t0cs bit) ............................... 119 interrupt .................................................................... 119 operation ................................................................. 119 prescaler. see prescaler, timer0. switching prescaler assignment .............................. 119 timer1 .............................................................................. 121 16-bit read/write mode ........................................... 124 associated registers ............................................... 125 interrupt .................................................................... 124 operation ................................................................. 122 oscillator .......................................................... 121 , 123 oscillator layout considerations ............................. 123 overflow interrupt ..................................................... 121 resetting, using a special event trigger output (ccp) ....................................... 124 special event trigger (ccp) .................................... 136 tmr1h register ...................................................... 121 tmr1l register ....................................................... 121 use as a real-time clock ....................................... 124 timer2 .............................................................................. 127 associated registers ............................................... 128 operation ................................................................. 127 postscaler. see postscaler, timer2. pr2 register .................................................... 127 , 138 prescaler. see prescaler, timer2. ssp clock shift ................................................ 127 , 128 tmr2 register ......................................................... 127 tmr2 to pr2 match interrupt .................. 127 , 128 , 138 timer3 .............................................................................. 129 associated registers ............................................... 131 operation ................................................................. 130 oscillator .......................................................... 129 , 131 overflow interrupt ............................................. 129 , 131 resetting, using a special event trigger output (ccp) ....................................... 131 tmr3h register ...................................................... 129 tmr3l register ....................................................... 129 timing diagrams a/d conversion ........................................................ 342 acknowledge sequence ........................................... 188 asynchronous reception ......................................... 205 asynchronous transmission .................................... 203 asynchronous transmission (back to back) ............ 203 baud rate generator with clock arbitration ............ 182 brg reset due to sda arbitration during start condition ...................................... 191 brown-out reset (bor) ........................................... 328 bus collision during a repeated start condition (case 1) .................................. 192 bus collision during a repeated start condition (case 2) .................................. 192 bus collision during a stop condition (case 1) ........................................................... 193 bus collision during a stop condition (case 2) ........................................................... 193 bus collision during start condition (scl = 0) .......................................................... 191 bus collision during start condition (sda only) ....................................................... 190 bus collision for transmit and acknowledge .................................................... 189 capture/compare/pwm (ccp) ............................... 330 clko and i/o .......................................................... 327 clock synchronization ............................................. 175 clock, instruction cycle ............................................. 57 example spi master mode (cke = 0) ..................... 332 example spi master mode (cke = 1) ..................... 333 example spi slave mode (cke = 0) ....................... 334 example spi slave mode (cke = 1) ....................... 335 external clock (all modes except pll) ................... 325 fail-safe clock monitor (fscm) .............................. 249 first start bit ............................................................ 183 full-bridge pwm output .......................................... 146 half-bridge pwm output ......................................... 145 i 2 c bus data ............................................................ 336 i 2 c bus start/stop bits ............................................ 336 i 2 c master mode (transmission, 7 or 10-bit address) ......................................... 186 i 2 c slave mode (transmission, 10-bit address) ...... 173 i 2 c slave mode (transmission, 7-bit address) ........ 171 i 2 c slave mode with sen = 0 (reception, 10-bit address) ............................. 172 i 2 c slave mode with sen = 0 (reception, 7-bit address) ............................... 170 i 2 c slave mode with sen = 1 (reception, 10-bit address) ............................. 177 i 2 c slave mode with sen = 1 (reception, 7-bit address) ............................... 176 low-voltage detect ................................................. 234 low-voltage detect characteristics ......................... 322 master ssp i 2 c bus data ........................................ 338 master ssp i 2 c bus start/stop bits ........................ 338 parallel slave port (pic18f4x20) ........................... 331 parallel slave port (psp) read ............................... 115 parallel slave port (psp) write ............................... 115 pwm auto-shutdown (prsen = 0, auto-restart disabled) .................................... 151 pwm auto-shutdown (prsen = 1, auto-restart enabled) ..................................... 151 pwm direction change ........................................... 148 pwm direction change at near 100% duty cycle ............................................. 148 pwm output ............................................................ 138 repeat start condition ............................................ 184 reset, watchdog timer (wdt), oscillator start-up timer (ost), power-up timer (pwrt) ................................. 328 slave mode general call address sequence (7 or 10- bit address mode) ............. 178 slave synchronization ............................................. 161 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................ 51 spi mode (master mode) ......................................... 160 spi mode (slave mode with cke = 0) ..................... 162 spi mode (slave mode with cke = 1) ..................... 162 stop condition receive or transmit mode .............. 188 synchronous transmission ..................................... 206 synchronous transmission (through txen) .......... 207 time-out sequence on por w/ pll enabled (mclr tied to v dd ) ..................... 51 time-out sequence on power-up (mclr not tied to v dd ): case 1 ....................... 50 time-out sequence on power-up (mclr not tied to v dd ): case 2 ....................... 50 time-out sequence on power-up (mclr tied to v dd , v dd rise t pwrt ) .............. 50
? 2003 microchip technology inc. ds39599c-page 381 pic18f2220/2320/4220/4320 timer0 and timer1 external clock .......................... 329 transition for entry to sec_idle mode .................... 34 transition for entry to sec_run mode .................... 36 transition for entry to sleep mode ............................ 32 transition for two-speed start-up (intosc to hspll) ......................................... 247 transition for wake from pri_idle mode ................. 33 transition for wake from rc_run mode (rc_run to pri_run) ..................................... 35 transition for wake from sec_run mode (hspll) ............................................................. 34 transition for wake from sleep (hspll) ................... 32 transition to pri_idle mode .................................... 33 transition to rc_idle mode ..................................... 35 transition to rc_run mode ..................................... 37 usart synchronous receive (master/slave) .................................................. 340 usart synchronous reception (master mode, sren) ...................................... 208 usart synchronoustransmission (master/slave) .................................................. 340 timing diagrams and specifications ................................ 325 a/d conversion requirements ................................ 342 capture/compare/pwm requirements ................... 330 clko and i/o requirements ................................... 327 dc characteristics - internal rc accuracy .............. 326 example spi mode requirements (master mode, cke = 0) .................................. 332 example spi mode requirements (master mode, cke = 1) .................................. 333 example spi mode requirements (slave mode, cke = 0) .................................... 334 example spi slave mode requirements (cke = 1) ......................................................... 335 external clock requirements .................................. 325 i 2 c bus data requirements (slave mode) .............. 337 master ssp i 2 c bus data requirements ................ 339 master ssp i 2 c bus start/stop bits requirements ................................................... 338 parallel slave port requirements (pic18f4x20) .... 331 pll clock ................................................................. 326 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ................ 328 timer0 and timer1 external clock requirements ................................................... 329 usart synchronous receive requirements ................................................... 340 usart synchronous transmission requirements ................................................... 340 top-of-stack access .......................................................... 54 trise register pspmode bit .......................................................... 109 tstfsz ............................................................................ 296 two-speed start-up ................................................. 237 , 247 two-word instructions example cases .......................................................... 58 txsta register brgh bit ................................................................. 198 u usart ............................................................................. 195 asynchronous mode ................................................ 202 associated registers, receive ........................ 205 associated registers, transmit ....................... 203 receiver .......................................................... 204 transmitter ...................................................... 202 baud rate generator (brg) ................................... 198 associated registers ....................................... 198 baud rate formula ......................................... 198 baud rates, asynchronous mode (brgh = 0, low speed) .......................... 199 baud rates, asynchronous mode (brgh = 1, high speed) ......................... 200 baud rates, synchronous mode (sync = 1) .............................................. 201 high baud rate select (brgh bit) ................. 198 operation in power managed mode ................ 198 sampling .......................................................... 198 serial port enable (spen bit) ................................. 195 setting up 9-bit mode with address detect ............. 204 synchronous master mode ...................................... 206 associated registers, reception ..................... 208 associated registers, transmit ....................... 207 reception ........................................................ 208 transmission ................................................... 206 synchronous slave mode ........................................ 209 associated registers, receive ........................ 210 associated registers, transmit ....................... 209 reception ........................................................ 210 transmission ................................................... 209 v voltage reference specifications .................................... 321 w watchdog timer (wdt) ............................................237 , 245 associated registers ............................................... 246 control register ....................................................... 245 during oscillator failure .......................................... 248 programming considerations .................................. 245 wcol .............................................................................. 183 wcol status flag ............................................ 183 , 185 , 188 www, on-line support ...................................................... 5 x xorlw ............................................................................ 296 xorwf ........................................................................... 297
pic18f2220/2320/4220/4320 ds39599c-page 382 ? 2003 microchip technology inc. notes:
? 2003 microchip technology inc. ds39599c-page 383 pic18f2220/2320/4220/4320 on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
pic18f2220/2320/4220/4320 ds39599c-page 384 ? 2003 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39599c pic18f2220/2320/4220/4320 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2003 microchip technology inc. ds39599c-page 385 pic18f2220/2320/4220/4320 pic18f2220/2320/4220/4320 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. part no. ? x /xx xxx pattern package temperature range device device pic18f2220/2320/4220/4320 (1) , pic18f2220/2320/4220/4320t (1,2) ; v dd range 4.2v to 5.5v pic18lf2220/2320/4220/4320 (1) , pic18lf2220/2320/4220/4320t (1,2) ; v dd range 2.0v to 5.5v temperature range i= -40 c to +85 c (industrial) package pt = tqfp (thin quad flatpack) so = soic sp = skinny plastic dip p=pdip ml = qfn pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf4320-i/p 301 = industrial temp., pdip package, extended v dd limits, qtp pattern #301. b) pic18lf2220-i/so = industrial temp., soic package, extended v dd limits. c) pic18f4220-i/p = industrial temp., pdip package, normal v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel ? soic and tqfp packages only.
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